J Korean inst Electromagn Sci Search


Journal of the Korean Institute of Electromagnetic and Science 2002;2(2):68-74.
Multilayer Power Delivery Network Design for Reduction of EMI and SSN in High-Speed Microprocessor System
Seong-Geun Park1, Ji-Seong Kim2, Jong-Gwan Yook1, Han-Kyu Park1
1Dept. of Electrical and Electronic Eng., Yonsei Univ.
2R&D Group, Computer Division, Samsung Electronics
In this paper, a pre-layout design approach for high-speed microprocessor is proposed. For multilayer PCB stark up configuration as well as selection and placement of decoupling capacitors, an effective solution for reducing SSN and EMI is obtained by modeling and simulation of complete power distribution system. The system model includes VRM, decoupling capacitors, multiple power and ground planes for core voltage, vias, as well as microprocessor. Finally, the simulation results are verified by measurements data.
Key words: Multilayer PCB, Power-Ground Plane, Resonance, Simultaneous Switching Noise, EMI, Simulation, Decoupling Capacitor, Microprocessor, Target Impedance, Computer System Design
Share :
Facebook Twitter Linked In Google+
METRICS Graph View
  • 235 View
  • 2 Download
Related articles in JEES


Browse all articles >

Editorial Office
#706 Totoo Valley, 217 Saechang-ro, Yongsan-gu, Seoul 04376, Korea
Tel: +82-2-337-9666    Fax: +82-2-6390-7550    E-mail: admin-jees@kiees.or.kr                

Copyright © 2019 by The Korean Institute of Electromagnetic Engineering and Science. All rights reserved.

Developed in M2community

Close layer
prev next