| A 9 mW Highly-Digitized 802.15.4 Receiver Using Bandpass ∑Δ ADC and IF Level Detection |
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Yong-Il Kwon1, Ta-Joon Park1, Hai-Young Lee2 |
1SAMSUNG Electro-Mechanics, Central R&D Institute
2Department of Electronics Engineering, Ajou University |
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| Abstract |
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A low power(9 mW) highly-digitized 2.4 GHz receiver for sensor network applications(IEEE 802.15.4 LR-WPAN) is realized by a $0.18{mu}m$ CMOS process. We adopted a novel receiver architecture adding an intermediate frequency (IF) level detection scheme to a low-power complex fifth-order continuous-time(CT) bandpass L:tl modulator in order to digitalize the receiver. By the continuous-time bandpass architecture, the proposed $SigmaDelta$ modulator requires no additional anti-aliasing filter in front of the modulator. Using the IF detector, the achieved dynamic range(DR) of the over-all system is 95 dB at a sampling rate of 64 MHz. This modulator has a bandwidth of 2 MHz centered at 2 MHz. The power consumption of this receiver is 9.0 mW with a 1.8 V power supply. |
| Key words:
Receiver$\Sigma\Delta$, ADC, Modulator, Bandpass Sigma Delta ADC, Complex Filter |
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