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J Electromagn Eng Sci > Volume 9(1); 2009 > Article
Journal of the Korean Institute of Electromagnetic and Science 2009;9(1):25-31.
DOI: https://doi.org/10.5515/JKIEES.2009.9.1.025   
Design Issues of CMOS VCO for RF Transceivers
Seong-Han Ryu
Department of Information and Communication Engineering, Hannam University
Abstract
This paper describes CMOS VCO circuit design procedures and techniques for multi-band/multi-standard RF transceivers. The proposed techniques enable a 4 GHz CMOS VCO to satisfy all requirements for Quad-band GSMIEDGE and WCDMA standards by achieving a good trade-off among important specifications, phase noise, power consumption, modulation performance, and chip area efficiency. To meet the very stringent GSM T/Rx phase noise and wide frequency range specifications, the VCO utilizes bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain(30$sim$50 MHz/V) and an on-chip $2^{nd}$ harmonic noise filter. The proposed VCO is implemented in $0.13{mu}m$ CMOS technology. The measured tuning range is about 34 %(3.17 to 4.49 GHz). The VCO exhibits a phase noise of -123 dBc/Hz at 400 kHz offset and -145 dBc/Hz at 3 MHz offset from a 900 MHz carrier after LO chain. The calculated figure of merit(FOM) is -183.5 dBc/Hz at 3 MHz offset. This fully integrated VCO occupies $0.45{times}0.9;mm^2$.
Key words: CMOS, Phase Noise, Wide Tuning Range, Complementary and NMOS Only Type VCO, Bondwire Inductor, Second Harmonic Filtering
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