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J Electromagn Eng Sci > Volume 14(2); 2014 > Article
Journal of Electromagnetic Engineering and Science 2014;14(2):68-73.
DOI: https://doi.org/10.5515/JKIEES.2014.14.2.68   
A CMOS Stacked-FET Power Amplifier Using PMOS Linearizer with Improved AM-PM
Unha Kim, Jung-Lin Woo, Sunghwan Park, Youngwoo Kwon
School of Electrical Engineering and Computer Science and INMC, Seoul National University
A linear stacked field-effect transistor (FET) power amplifier (PA) is implemented using a $0.18-{mu}m$ silicon-on-insulator CMOS process for W-CDMA handset applications. Phase distortion by the nonlinear gate-source capacitance ($C_{gs}$) of the common-source transistor, which is one of the major nonlinear sources for intermodulation distortion, is compensated by employing a PMOS linearizer with improved AM-PM. The linearizer is used at the gate of the driver-stage instead of main-stage transistor, thereby avoiding excessive capacitance loading while compensating the AM-PM distortions of both stages. The fabricated 836.5 MHz linear PA module shows an adjacent channel leakage ratio better than -40 dBc up to the rated linear output power of 27.1 dBm, and power-added efficiency of 45.6% at 27.1 dBm without digital pre-distortion.
Key words: CMOS, Linear, Power Amplifier (PA), Stacked-FET, W-CDMA


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