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J Electromagn Eng Sci > Volume 14(4); 2014 > Article
Journal of Electromagnetic Engineering and Science 2014;14(4):376-381.
DOI: https://doi.org/10.5515/JKIEES.2014.14.4.376   
Slew-Rate Enhanced Low-Dropout Regulator by Dynamic Current Biasing
Nam Hwi Jeong, Choon Sik Cho
Department of Information and Telecommunication Engineering, Korea Aerospace University
We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.
Key words: Dynamic Current Biasing, Low-Dropout Regulator, Parasitic Capacitance, Slew-Rate
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