J Electromagn Eng Sci Search

CLOSE


J Electromagn Eng Sci > Volume 17(2); 2017 > Article
Journal of Electromagnetic Engineering and Science 2017;17(2):98-104.
DOI: https://doi.org/10.5515/JKIEES.2017.17.2.98   
CMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies
Junghwan Yoo, Jae-Sung Rieh
School of Electrical Engineering, Korea University
Correspondence:  Jae-Sung Rieh,Email: jsrieh@korea.ac.kr
Abstract
This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84-122.61 GHz and 126.53-129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are -8.6 dBm and -10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. Th e measured phase noise of PLL1 is -59.2 at 10 kHz offset and -104.5 at 10 MHz offset, and the phase noise of PLL2 is -60.9 dBc/Hz at 10 kHz offset and -104.4 dBc/Hz at 10 MHz offset. The chip sizes are $1,080{mu}m{times}760{mu}m$ (PLL1) and $1,100{mu}m{times}800{mu}m$ (PLL2), including the probing pads.
Key words: CMOS, Frequency Doubler, Phase-Locked Loop (PLL), Signal Source, Voltage-Controlled Oscillator (VCO)
TOOLS
Share :
Facebook Twitter Linked In Google+
METRICS Graph View
  • 1 Crossref
  • 0 Scopus
  • 157 View
  • 6 Download
Related articles in JEES

ABOUT
ARTICLE CATEGORY

Browse all articles >

BROWSE ARTICLES
AUTHOR INFORMATION
Editorial Office
#706 Totoo Valley, 217 Saechang-ro, Yongsan-gu, Seoul 04376, Korea
Tel: +82-2-337-9666    Fax: +82-2-6390-7550    E-mail: admin-jees@kiees.or.kr                

Copyright © 2018 by The Korean Institute of Electromagnetic Engineering and Science. All rights reserved.

Developed in M2community

Close layer
prev next