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J. Electromagn. Eng. Sci > Volume 22(4); 2022 > Article
Lee, Lee, Kim, and Cho: SAR ADC for a Multimode Radar Transceiver with Offset Calibration

Abstract

In this paper, we design a successive approximation register (SAR) analog-to-digital converter (ADC) suitable for multimode radar transceivers. For multimode radars, the sampling rate required by ADC varies according to the continuous wave (CW) or frequency modulated continuous wave (FMCW) used for operation. Therefore, depending on which waveform is used, the input is designed to enter two paths. For path 1, we obtained 9.23 bits of effective number of bits (ENOB), 57.35 dB of signal-to-noise distortion ratio (SNDR), and 64.62 dB of spurious free dynamic range (SFDR), and the power consumption was 0.3481 mW, resulting in a figure-of-merit (FOM) of 28.9 fJ/Conv-Step. On path 2, we obtained an 8.97 bit of ENOB, 55.76 dB of SNDR, and 60.53 dB of SFDR, and the power consumption was 1.72 μW, resulting in a FOM of 34.2 fJ/Conv-Step. Further, a circuit was constructed to reduce the offset of the comparator. As a result of 100 Monte Carlo simulations, the offset was reduced from −46 mV/+50 mV to −4 mV/+4 mV when the worst case was considered.

I. Introduction

Recently, the demand for military or civilian drones and surveillance radars has been increasing. In radar transceivers, several forms of waves are used to determine object distance and velocity information, of which continuous wave (CW) and frequency modulated continuous wave (FMCW) are typically used [13]. If CW is used, the speed of the object can be determined but not the distance. When using FMCW, both the distance and speed of the object can be determined, but when there are multiple targets, a ghost target is created.
To solve this problem, FMCW and CW can be used together to verify the distance and speed information of multiple targets without a ghost target [2]. For CW, the Doppler frequency is added to the carrier frequency and received by the receiver, whereas for FMCW, the additional beat frequency, as well as the Doppler frequency, is received; therefore, for each case, the sampling rate required by the analog-to-digital converter (ADC) is different. If the sampling rate is high, it is advantageous that the switch size is large and the capacitor size is small. However, if the sampling rate is low, it is advantageous that the size of the capacitor is large, and the size of the switch is small, considering the charge injection and clock feed-through. Therefore, this work proposes a design that uses different sample-and-hold circuits when using FMCW and CW.
In ADC, the sample-and-hold circuit, and the capacitive digital-to-analog converter (CDAC) are mainly used together. That is, the CDAC acts as a capacitor for the sample and hold circuits. However, in the case of CDAC, the small design of unit capacitors will have a negative impact on performance because matching characteristics have a very large impact on linearity.
Eq. (1) represents the resistance of the switch when the switch is designed as NMOS, as shown in Fig. 1, and Eq. (2) shows the error in the output of the sample-and-hold considering the charge injection.
(1)
RON=1(μnCoxW/L)(VGS-VTH),
(2)
ΔV=WLCox(VDD-Vin-VTH)2CH.
Eq. (1) and Eq. (2) show that there is a trade-off relationship between RON and charge injection, depending on the size of the switch [4]. Fig. 2 shows the spurious free dynamic range (SFDR) according to the input frequency and size of the CMOS switch. The sampling rate is based on Nyquist sampling. If the sampling rate is high, the larger switch provides a higher signal-to-noise distortion ratio (SNDR), and if the sampling rate is low, the smaller switch provides a higher SNDR.
Therefore, in this work, when using FMCW, the switch’s clock was bootstrapped, and the sampling capacitor was used separately. When using CW, a small switch was used, and CDAC was designed to act as a capacitor for the sample-and-hold circuits.
Further, the DC offset of ADC, which causes errors in distance or speed, is eliminated primarily by signal processing in DSPs; however, in this work, we designed circuits that calibrate offset in analog-integrated circuits. In general, offset calibration in the comparator includes auto-zeroing [5], which is a method of sampling offset charge, or a method of compensating Vth mismatch by changing the body voltage on both sides of the input MOSFET through a charge pump and phase detector [6].
However, in the case of auto-zeroing, the successive approximation register (SAR) ADC requires a preamp with a high gain, which slows the ADC’s operating speed. The disadvantage of changing body voltage is that if the offset is too large, too much change in body voltage can lead to leakage from the body to the source or body to drain, and the addition of a switch used in offset calibration mode slows the capacitor down. To overcome these shortcomings, this paper calibrates offset using a method of changing Vref.
The remainder of this paper is organized as follows: Section II describes the structure of the proposed ADC and the description of each block, Section III describes the simulation results, and Section IV concludes this paper.

II. Architecture and Circuit Description

Fig. 3 shows the block diagram of the SAR ADC. First, in the offset calibration phase, the SAR control logic does not work, and the offset of the comparator is calibrated. As shown in Eq. (3), the offset can be reduced if the input MOSFET is large [7].
(3)
VOffset(ΔVth1,2)2+{(Vgs-Vth)1,22(ΔWL1,2WL1,2)}2+(ΔVth3,4)2+{(Vgs-Vth)3,42(ΔWL3,4WL3,4)}2.
However, there are two disadvantages to designing an input MOSFET large. First, the kickback noise caused by the clock of the comparator increases. Second, the CDAC produces a gain error equal to CS/(CS+CP). In particular, the size of the sampling capacitor used in the FMCW mode was smaller in this work, which is more fatal. Therefore, the size of the input MOSFET is designed to be calibrated instead of the small size of the input MOSFET designed to be calibrated.
In the A/D conversion phase, the offset calibration logic does not work, and the differential input signal enters two paths, and the magnitude of the output voltage at paths 1 and 2 determines the output of the comparator. In the FMCW mode, the input enters path 1, and the input switch in path 2 is designed to always be open. At this point, the sampled input in path 1 is output, and at path 2, the voltage that is feedback through the comparator, control logic, and CDAC is output. Conversely, in the CW mode, the input enters path 2, the input switch in path 1 is always open, and the output of path 1 is always designed to be common-mode voltage (VCM). In path 2, the sampled input and the voltage from the CDAC are added to the output. In both paths 1 and 2, input is sampled using the bottom plate sampling technique, in CDAC in path 2, VCM based switching is used to reduce area and energy consumption, and a bridge capacitor is used. Further, in path 1, the switch uses a bootstrap circuit to sample fast inputs, and in path 2, a transmission gate switch with a simpler structure and less power consumption than the bootstrap circuit is used because it does not sample fast inputs.
Fig. 4 shows a schematic of the bootstrap circuit. In the track-and-hold circuit, the sampling speed is determined by the value of the RON of the MOSFET and the value of the sampling capacitor. If only a simple NMOS is used as a switch, it causes nonlinearity that changes Vgs according to Vin. However, the use of bootstraps can prevent RON’s value from changing as Vin changes by fixing the value of Vgs [8]. However, as shown in Eq. (4), the change in Vth caused by the body effect follows the change in Vin.
(4)
Vth=Vth0+γ(2F+Vsb-2F).
The change in Vth causes a change in Ron and a change in charge injection [9]. To prevent the Vth from changing due to the body effect, the body is connected to the Vin during the sampling phase. In the hold phase, the body is connected to the ground to prevent leakage from the body to the output.
Fig. 5 is a schematic of the comparator designed with four inputs based on a double tail current comparator [10]. The double-tail current comparator is more advantageous than the commonly used strong-arm latch in terms of current consumption, delay, and offset compared to the commonly used strong-arm latch.
Fig. 6 shows a circuit diagram of the CDAC. Vcm-based switching technique is used to reduce the area and switch energy consumption, and the total area is greatly reduced using bridge capacitors [11]. The size of the bridge capacitor is equal to that of the unit capacitor.
Fig. 7 shows a block diagram of the offset calibration. We propose a method for offset calibration by controlling the reference voltage according to the output result of the comparator in the offset calibration phase. If offset is present, the action is to bring the values of Vref,n close to Vref,p + Voffset, as shown in Fig. 8.
Fig. 9(a) shows a circuit diagram of the offset control logic, and Fig. 9(b) shows a circuit diagram of the reference voltage with the switch. If offset is present, the offset is compensated by increasing Vref,n, or Vref,p according to the output of the comparator. Fig. 10 shows Vref,n following Vref,p when the offset is modeled at 10 mV using an ideal source of voltage without a mismatch.
Before and after calibration, a Monte Carlo simulation was carried out to check the offset of the capacitor. As shown in Fig. 11, the offset of the comparator before calibration was −46 mV and 50 mV in the worst case. By contrast, after calibration, the offset was −4 mV and 4 mV in the worst case. Table 1 compares offsets before and after calibration.

III. Simulation Result

Fig. 12 shows the results of the fast Fourier transform (FFT) simulation of the designed ADC. This result is a pre-simulation result, but a capacitance of 5 fF was applied to the intermediate node of each block in consideration of the value of parasitic capacitance that may occur during the layout. Fig. 12(a) is obtained when the input enters path 1, and the input frequency is determined to be close to 10 MHz, considering coherent sampling. Fig. 12(b) shows that the input enters path 2, and the input frequency is similarly determined to be around 50 kHz, considering coherent sampling. Simulation results show that if the input enters path 1, it obtains an SFDR of 64.62 dB, an SNDR of 57.35 dB, and an effective number of bits (ENOB) of 9.23 bits. Power consumption is 0.3481 mW, and figure-of-merit (FOM) is 28.9 fJ/Conv-Step. If the input enters path 2, it obtains an SFDR of 60.53 dB, an SNDR of 55.76 dB, and an ENOB of 8.97 bits. Power consumption is 1.72 μW and FOM is 34.2 fJ/Conv-Step. Tables 2 and 3 compare performance with other works [1217]. As shown in the tables, the ADC proposed in this work uses two different input paths according to the input frequencies, so it does not degrade the SNDR or SFDR compared to ADCs with different sampling rates.

IV. Conclusion

This paper shows the design results in the TSMC 65 nm process and uses a supply voltage of 1.2 V. We designed a suitable SAR ADC for multimode radar transceivers. In both modes, inputs are designed to fit in different paths, both with a resolution of 10 bits. The ADC was designed to operate at sampling rates of 20 MS/s and 100 kS/s, respectively, and when Nyquist sampling was performed, path 1 obtained an SFDR of 64.62 dB, an SNDR of 57.35 dB, and an ENOB of 9.23 bits. Power consumption was 0.3481 mW, and FOM was 28.9 fJ/Conv-Step. In the case of path 2, SFDR was 60.53 dB, SNDR was 55.76 dB, ENOB was 8.97 bits, power consumption was 1.72 μW and FOM was 34.2 fJ/Conv-Step. The design also configured a circuit for offset calibration of the comparator to reduce the offset from −46 mV/+50 mV to −4/+4 mV in the worst case.

Acknowledgments

This work was supported by the Institute for Information & Communications Technology Promotion (IITP) grant funded by the Korean government (MSIT) (No. 2017-0-00528, The Basic Research Lab for Intelligent Semiconductor Working for the Multi-Band Smart Radar).

Fig. 1
Sample-and-hold using NMOS as a switch.
jees-2022-4-r-105f1.jpg
Fig. 2
SFDR by input frequency and switch size.
jees-2022-4-r-105f2.jpg
Fig. 3
Block diagram of the proposed SAR ADC.
jees-2022-4-r-105f3.jpg
Fig. 4
Schematic of the bootstrap circuit.
jees-2022-4-r-105f4.jpg
Fig. 5
Schematic of the comparator.
jees-2022-4-r-105f5.jpg
Fig. 6
CDAC with a split capacitor.
jees-2022-4-r-105f6.jpg
Fig. 7
Block diagram of offset calibration.
jees-2022-4-r-105f7.jpg
Fig. 8
Flowchart of offset calibration.
jees-2022-4-r-105f8.jpg
Fig. 9
(a) Offset control logic and (b) reference voltage with switch.
jees-2022-4-r-105f9.jpg
Fig. 10
Calibrated offset using Vref change.
jees-2022-4-r-105f10.jpg
Fig. 11
Monte Carlo simulation results.
jees-2022-4-r-105f11.jpg
Fig. 12
Simulated frequency spectrum on (a) path 1 and (b) path 2.
jees-2022-4-r-105f12.jpg
Table 1
Offset statics without and with calibration (unit: mV)
Calibration

Before After
Mean of absolute offset 14.78 1.54
Min offset −46 −4
Max offset 50 4
Table 2
Comparison of SAR ADC with a comparable sampling rate when using path 1
This work (path 1)a Kim et al. [12] Liu et al. [13] Chung et al. [14]
Technology (nm) 65 65 130 130
Supply voltage (V) 1.2 0.6 1.2 1.2
Resolution (bit) 10 12 10 12
Sampling rate (S/s) 20M 10M 50M 40M
SNDR (dB) 57.35 64.3 52.8 62.5
SFDR (dB) 64.62 83.8 - 73
ENOB (dB) 9.23 10.4 8.48 10.08
Power (mW) 0.3481 0.083 0.92 1.32
FOM (fJ/Conv-Step) 28.9 6.2 52 30.4

a Pre-simulation result.

Table 3
Comparison of SAR ADC with comparable sampling rates when using path 2
This work (path 2)a Sadollahi et al. [15] Xie et al. [16] Tang et al. [17]
Technology (nm) 65 180 130 65
Supply voltage (V) 1.2 0.75 3.3 0.9
Resolution (bit) 10 11 10 10
Sampling rate (S/s) 100k 10k 100k 1k
SNDR (dB) 55.76 60.5 60.4 56.5
SFDR (dB) 60.53 72 69.2 75.3
ENOB (dB) 8.97 9.76 9.75 9.1
Power (mW) 1.72 0.25 8.25 0.0058
FOM (fJ/Conv-Step) 34.2 28.8 95.8 10.94

a Pre-simulation result.

References

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Biography

jees-2022-4-r-105f13.jpg
Jin-Seop Lee received his B.S. and M.S. degrees from the Department of Electrical Engineering, Korea Aerospace University, Goyang, Korea, in 2020 and 2022, respectively. His research interests include the design of RFIC, data converters, and radar systems.

Biography

jees-2022-4-r-105f14.jpg
Hyun-Yeop Lee received his B.S. degrees from the Department of Electrical Engineering, Korea Aerospace University, Goyang, Korea in 2021. His research interests include the design of RFIC, data converters, and radar systems.

Biography

jees-2022-4-r-105f15.jpg
Young-Jin Kim received his B.S. degree in electrical engineering from Kyungpook National University in 1995. He received M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST) in 1997 and 2002, respectively. His Ph.D. dissertation focused on the transceiver architecture of image rejection and spurious rejection. In 2002, he joined Samsung Electronics Co. Ltd., Korea, as a senior engineer. Since then, he has participated in the design of CDMA and GSM/GPRS wireless mobile applications. Furthermore, he designed an LNA and down-conversion mixer for multimode CDMA and GSM/GPRS. In 2006, he joined the School of Electronics and Information Engineering, Korea Aerospace University, Goyang, Korea.

Biography

jees-2022-4-r-105f16.jpg
Choon-Sik Cho received his B.S. in Control and Instrumentation Engineering from Seoul National University in 1987, his M.S. in Electrical and Computer Engineering from the University of South Carolina in 1995, and his Ph.D. in Electrical and Computer Engineering from the University of Colorado in 1998. From 1987 to 1993, he worked at LG Electronics with a focus on communication systems. From 1999 to 2003, he worked for Curitel, where he was principally involved in the development of mobile phones. He joined the School of Electronics and Information Engineering at Korea Aerospace University in 2004. His research interests include the design of RFIC/MMIC, millimeter-wave ICs, analog circuits, and radar systems.
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