A Folded Cascode CMOS Low Noise Amplifier with Transformer Feedback

Article information

J. Electromagn. Eng. Sci. 2024;24(1):57-64

Publication date (electronic) : 2024 January 31

doi : https://doi.org/10.26866/jees.2024.1.r.205

Dongmyeong Kim¹, Haseon Song¹, Ilku Nam^2,, Donggu Im^1,

¹Division of Electronic Engineering, Jeonbuk National University, Jeonju, Korea

²Department of Electrical Engineering and PNU-LG Electronics Smart Control Center, Pusan National University, Busan, Korea

^*Corresponding Author: Ilku Nam (nik@pusan.ac.kr), Donggu Im (dgim@jbnu.ac.kr)

Received 2023 April 18; Revised 2023 June 29; Accepted 2023 August 1.

Abstract

I. INTRODUCTION

Internet-of-Things (IoT) technologies connect devices, people, data, and processes across a wide range of applications, including healthcare, home automation, energy management, and environmental monitoring. Notably, the backbones of these highly reliable IoT systems are the various available wireless technologies (ZigBee, BLE, MBAN, and Wi-Fi). Among these, Wi-Fi has become a ubiquitous choice, as it supports an extremely diverse array of profiles while consuming varying levels of power and providing wide communication coverage. This is the consequence of the proliferation of its family of standards.

Since the 2.4-GHz ISM band is crowded by multiple strong sources of interference, such as cellular phones and CCTVs, Wi-Fi receivers need to be highly linear so as to minimize the degradation of the signal-to-noise-and-distortion ratio caused by inter-modulation, cross-modulation, saturation, and desensitization. In particular, the linearity burden in modern RF receivers pertains to the first building block of the low noise amplifier (LNA), since surface acoustic wave (SAW)-less techniques, such as the N-path filter from [1, 2], provide a high selectivity RF bandpass response with a very accurate center frequency set by the local oscillator, thus relaxing the linearity requirement of the subsequent building blocks (mixer, baseband analog chain, and analog-to-digital converter). Although various linearization techniques have been developed to improve the input-referred third-order intercept point (IIP3) of the LNA [3, 4], most are extremely sensitive to variations in process-temperature-voltage (PVT), and ultimately fail to improve large signal linearity, such as the input 1-dB compression point (P1dB) and blocker-induced noise figure (NF). In sum, an LNA with Wi-Fi applications should exhibit high input P1dB and IIP3 while maintaining a low NF of around 1 dB. This challenge becomes even more acute with the scaling down of the channel length of MOSFET devices due to the low supply voltage. In this paper, a folded cascode inductive source degeneration LNA (ISDLNA) with transformer feedback is proposed to simultaneously improve input P1dB and IIP3 without sacrificing NF performance and silicon area.

The remainder of this paper is structured as follows: Section II reviews conventional cascode and folded cascode ISDLNAs, while Section III presents an analysis of the input impedance, power gain, and NF of the proposed LNA. Following this, Section IV presents the design of the transformer and the completed LNA. The experimental results obtained on testing the proposed LNA are reported in Section V. Finally, Section VI presents the conclusions of this research.

II. REVIEW OF CONVENTIONAL CASCODE AND FOLDED CASCODE ISDLNAS

Fig. 1(a) depicts a conventional cascode ISDLNA used in a wide array of commercial narrowband receiver applications. These conventional ISDLNAs achieve excellent NF performance due to their simultaneous noise and input impedance matching. However, the relatively large voltage headroom used by the stacking topology of their common source (CS) and common gate (CG) transistors severely limits the output voltage swing under low supply voltage (VDD) conditions, resulting in poor input P1dB of the LNA. The drain-to-source dc bias voltage (V_DS) of the CS and CG transistors in the cascode structure is approximately half of VDD, which means that the drain conductance (g_ds) nonlinearity of the CG transistor caused by the lower V_DS can no longer be ignored. This causes additional IIP3 degradation. Additionally, as the operating frequency and gain increase, the CG stage limits the linearity of the LNA due to parasitic junction capacitance, including the drain-to-source capacitance of the CS transistor, gate-to-source capacitance, and the finite output resistance of the CG transistor [5].

Fig. 1

Schematics of (a) conventional cascode inductive source degenerated LNA (ISDLNA) and (b) folded cascode ISDLNA.

To overcome the drawbacks of the conventional cascode ISDLNA, a folded cascode ISDLNA, as depicted in Fig. 1(b), was reported in [6, 7]. The V_DS of all transistors was set close to VDD due to the absence of the stacking gain stage (CG transistor), enabling the folded cascode ISDLNA to achieve exclusive advantages in terms of P1dB and IIP3. Furthermore, since a PMOS transistor typically exhibits higher output resistance than an NMOS transistor under the same channel length conditions, this mitigates the IIP3 degradation caused by the g_ds nonlinearity of the CG transistor. Some improvement in IIP3 can also be achieved through distortion cancellation by controlling the size and dc bias voltage of the CG transistor and canceling out the nonlinearities of the NMOS and PMOS transistors [8]. However, such an LNA requires a larger silicon area than a conventional cascode ISDLNA, owing to the inclusion of a folding inductor that operates as an RF choke.

III. ANALYSIS OF THE PROPOSED FOLDED CASCODE ISDLNA WITH TRANSFORMER FEEDBACK

Fig. 2 presents the proposed folded cascode ISDLNA with transformer feedback. An external matching network composed of two off-chip inductors (L_p and L_g), was adopted to achieve simultaneous noise and input impedance matching with minimal signal loss. To reduce the silicon area occupied by the onchip inductors, the transformer feedback was implemented by introducing magnetic coupling between the source inductor (L_s) and the folding inductor (L₁), representing the primary and secondary coils of the transformer, respectively. These two coils had the same polarity, allowing them to form negative feedback. This transformer feedback effectively cancelled the Miller capacitance (gate-to-drain capacitance [C_gd]), neutralized the amplifier, and improved the linearity. In contrast to conventional resistive feedback or active feedback LNAs, in which the feedback network directly degrades the overall NF of the LNA, the proposed transformer feedback LNA minimized the NF degradation caused by the feedback network due to the realization of noiseless feedback between the two existing inductors. However, this transformer feedback requires detailed analysis regarding the effect of the qualify factor (Q-factor) and the coupling coefficient of the on-chip transformer on the input impedance (Z_in), power gain (S₂₁), and NF of the amplifier.

Fig. 2

Schematic of the proposed folded cascode ISDLNA with transformer feedback. The channel length of all MOSFETs is 130-nm. The gate-to-source capacitance (C_gs1) is the sum of the intrinsic C_gs1 and any extra added capacitance. The capacitance C₁ includes all node-to-substrate parasitic capacitances caused by MOSFETs as well as any extra added capacitance. The capacitance C_big is an ac-coupling capacitor.

1. Input Impedance

Fig. 3 presents a small-signal equivalent circuit model of the proposed LNA, where i₁ and i₂ denote the alternating current (ac) flowing into the primary and secondary coils, respectively. Meanwhile, the effect of the transformer’s magnetic coupling is modeled as two current sources. The transformer turn ratio and coupling coefficient are denoted by n and k, respectively. Considering that the parallel L₁//C₁ circuit resonates at the operating frequency (ω₀), the approximate Z_in of the proposed LNA is calculated as follows:

Fig. 3

Small-signal equivalent circuit model of the proposed folded cascode ISDLNA with transformer feedback. The R_Lp, R_Lg, R_Ls, R_L1, and R_Ld denote the series or parallel resistances resulting from the finite Q-factor of the inductors.

(1) Zin≈(jω0Lp+RLp)//{jω0(Lg+Lb)+RLg+Rb+(Zin1//1jω0Cp)},where Zin1≈LsCgs1{gm1(1+nk)-k(n+k)Rm2}+RLs{1-k(n+k)C1Cgs1}+jω0Ls{1-k(n+k)C1Cgs1}+RLsjω0Cgs1{1RLs+gm1(1+nk)-k(n+k)Zcas.M2}and Cp≈(LgLg+Lb+1)Cb+(2+kn)Cgd1,Zcas.M2≈Rd+ro21+gm2ro2,

where g_m1 and g_m2 represent the transconductances of M₁ and M₂, respectively. Furthermore, r_o1 and r_o2 denote the output resistances of M₁ and M₂, while Z_in1 and Z_cas.M2 are the impedances looking into the gate node of M₁ and the source node of M₂ at the operating frequency, respectively. Meanwhile, R_d indicates the effective resistance of R_Ld and R_s/(ω₀C_oR_s)² in parallel, and C_p includes the effect of the Miller capacitance (C_gd1) of M₁. The effect of the bond wire is also considered for calculating the Z_in. Similar to the conventional cascode ISDLNA presented in Fig. 1(a), the real and imaginary parts of the Z_in of the proposed LNA can be independently tuned by L_p, L_g, and L_s. The reactive parts were canceled at ω₀, while the real part was set equal to the source resistance (R_s) for input impedance matching. In this design, considering the variations in Z_in1, an input impedance matching network composed of L_p and L_g was designed to achieve an input return loss (S₁₁) of less than −10 dB with a low NF across a wide range of k, as shown in Fig. 4.

Fig. 4

Calculated input return loss (S₁₁), S₂₁, and NF of the proposed LNA according to variations of k of the transformer. The design parameters extracted from the foundry’s process design kit were used for this calculation.

IV. DESIGN OF THE TRANSFORMER AND THE COMPLETED LNA

Fig. 5 shows the physical layout of the designed transformer. To achieve a high Q-factor, ultra-thick metal (UTM) provided by the adopted process technology was used. The transformer was designed to have an n of 2 and k of 0.8 to optimize its key performances, such as Z_in, S₂₁, and NF. The line width was 9- μm, the space between lines was 3-μm, and the inner radius was 290-μm. The number of turns in the primary and secondary coils was 2 and 4, respectively. Fig. 6 presents the EM simulation results (inductance, Q-factor, and coupling coefficient) of the designed transformer, which was simulated using a 3D High-Frequency Simulation Software (HFSS) simulation tool. The thickness and resistivity of the handle wafer were 700 μm and 1 kΩ·cm, respectively. The UTM was made of aluminum (Al), and its thickness was 4.1 μm. At an operating frequency of 2.4 GHz, the inductance and Q-factor of the primary coil (secondary coil) were approximately 0.9 nH and 2.4 (3.2 nH and 2.4). The simulated k was about 0.89 at an operating frequency of 2.4 GHz.

Fig. 5

Physical layout of the designed transformer.

Fig. 6

Electromagnetic simulation results of the designed transformer: (a) inductance, Q-factor, and (b) coupling coefficient.

Fig. 7 presents the pre-layout simulation results, post-layout simulation results, and calculation results of the completed LNA. Notably, the post-layout simulation included the effects of input/output (I/O) pads and electrostatic discharge (ESD) diodes. The designed LNA exhibits pre-layout simulated S₂₁, S₁₁, and NF values of 19.5 dB, −10.7 dB, and 1.2 dB, and post-layout simulated S₂₁, S₁₁, and NF values of 16.5 dB, −9.5 dB, and 1.4 dB, respectively. It is further observed that the pre-layout simulation results, which excluded the IO pads, ESD diodes, and parasitic components of the metal wires are well matched with the calculation results.

Fig. 7

Pre-layout simulation results, post-layout simulation results, and calculation results of the completed LNA.

V. EXPERIMENTAL RESULTS

The proposed folded cascode ISDLNA with transformer feedback was implemented using a DB HiTek 0.13-μm RF CMOS process. Fig. 8 shows photographs of the conventional cascode ISDLNA from Fig. 1(a) and the proposed LNA from Fig. 2. The conventional cascode ISDLNA was implemented using the same process technology so as to directly compare its performance to that of the proposed LNA. Excluding the IO pads, the chip areas of the conventional cascode ISDLNA and the proposed LNA were approximately 0.2 mm² and 0.3 mm², respectively.

Fig. 8

Photographs of the implemented chips: (a) conventional cascode ISDLNA illustrated in Fig. 1(a); and (b) the proposed LNA presented in Fig. 2.

Fig. 9 presents the measured S-parameters, NF, IIP3, and input P1dB of both LNAs. To ensure a fair comparison, the power consumption of both LNAs was set at 9.6 mW, drawn from a 1.2-V supply voltage. The two-tone spacing for the measurement of IIP3 was 10 MHz. The conventional cascode ISDLNA showed an S₂₁ of 15.7 dB, an NF of 1.1 dB, an IIP3 of −8.5 dBm, an output-referred third-order intercept point (OIP3) of +7.2 dBm, and an input P1dB of −14 dBm, while achieving an S₁₁ of less than −10 dB at an operating frequency of 2.4 GHz. In contrast, the proposed LNA exhibited an S₂₁ of 11.0 dB, an NF of 2.6 dB, an IIP3 of +2.5 dBm, an OIP3 of +13.5 dBm, and an input P1dB of −5.6 dBm while achieving an S₁₁ of −7 dB at the operating frequency of 2.4 GHz. As predicted, the proposed LNA significantly improved OIP3 and input P1dB with nearly the same power consumption and chip area compared to the conventional cascode ISDLNA. These results may be attributed to the inherently high linearity characteristic of the folded cascode topology. In addition, considering the simulated OIP3 of the folded cascode LNAs obtained with and without the transformer feedback, an additional OIP3 improvement of about 2 dB was observed when using the transformer feedback. Unfortunately, a peak gain degradation of 6 dB and an average NF degradation of 1.1 dB were observed in the experimental measurements which were not seen in the post-layout simulation. The main reason for this degradation could be the shifted resonance frequency of L₁ and C₁ from 2.4 GHz, resulting from an inaccurate EM simulation of the transformer.

Fig. 9

Measured RF performances of the conventional cascode ISDLNA and the proposed LNA: (a) S-parameters, NF, and (b) IIP3.

Table 1 compares the performance of the proposed LNA to that reported in previous works [10–14]. The figure-of-merit (FoM) is derived in accordance with [15], as follows:

Table 1

Performance summary and comparison

where P_dc refers to dc power dissipation. Compared to previous works, including the conventional cascode ISDLNA, the proposed LNA achieves a higher OIP3 and input P1dB with comparable NF performance due to its folded cascode topology and the transformer feedback. Moreover, the silicon area occupied by the proposed LNA is nearly identical to that used by the conventional cascode ISDLNA.

VI. CONCLUSION

A folded cascode CMOS LNA with transformer feedback was proposed for use in wireless local area network front-end module applications. Compared to previous works, including a conventional cascode ISDLNA, the proposed LNA significantly improved the IIP3 and input P1dB with exhibiting a somewhat degraded NF, while also saving silicon area by magnetically coupling the source and folding inductors. In terms of experimental results, the proposed LNA exhibited an S₂₁ of 11.0 dB, an NF of 2.6 dB, an IIP3 of +2.5 dBm, an OIP3 of +13.5 dBm, and an input P1dB of −5.6 dBm while also achieving an S₁₁ of −7 dB at the operating frequency of 2.4 GHz. The power consumption was 9.6 mW from a 1.2-V supply voltage.

Article information Continued