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J Electromagn Eng Sci > Volume 17(3); 2017 > Article
Journal of Electromagnetic Engineering and Science 2017;17(3):138-146.
DOI: https://doi.org/10.5515/JKIEES.2017.17.3.138    Published online July 31, 2017.
New Configuration of a PLDRO with an Interconnected Dual PLL Structure for K-Band Application
Yuseok Jeon1, Sungil Bang2
1Research and Development Department, Broadern Inc., Hwaseong, Korea
2Division of Electronic and Electric Engineering, Dankook University, Yongin, Korea.
Correspondence:  Yuseok Jeon,Email: halsuida@naver.com
Received: 21 March 2017   • Revised: 7 June 2017   • Accepted: 11 July 2017
Abstract
A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.
Key words: Analog PLL, Digital PLL, Dual-Loop, Front-End, Phase-Locked PLL, PLDRO

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