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J. Electromagn. Eng. Sci > Volume 14(4); 2014 > Article
Journal of Electromagnetic Engineering and Science 2014;14(4):393-398.
DOI: https://doi.org/10.5515/JKIEES.2014.14.4.393   
A Highly Efficient Dual-Mode 3G/4G Linear CMOS Stacked-FET Power Amplifier Using Active-Bypass
Unha Kim, Yong-Gwan Kim, Jung-Lin Woo, Sunghwan Park, Youngwoo Kwon
School of Electrical Engineering and Computer Science and INMC, Seoul National University
A highly efficient dual-mode linear CMOS stacked-FET power amplifier (PA) is implemented for 3G UMTS and 4G LTE handset applications. High efficiency is achieved at a backed-off output power ($P_{out}$) below 12 dBm by employing an active-bypass amplifier, which consumes very low quiescent current and has high load-impedance. The output paths between high- and low-power modes of the PA are effectively isolated by using a bypass switch, thus no RF performance degradation occurs at high-power mode operation. The fabricated 900 MHz CMOS PA using a silicon-on-insulator (SOI) CMOS process operates with an idle current of 5.5 mA and shows power-added efficiency (PAE) of 20.5%/43.5% at $P_{out}$ = 12.4 / 28.2 dBm while maintaining an adjacent channel leakage ratio (ACLR) better than -39 dBc, using the 3GPP uplink W-CDMA signal. The PA also exhibits PAE of 35.1% and $ACLR_{E-UTRA}$ of -33 dBc at $P_{out}$ = 26.5 dBm, using the 20 MHz bandwidth 16-QAM LTE signal.
Key words: Active-Bypass, CMOS, Efficiency, Linear, LTE, Power Amplifier, Stacked-FET, W-CDMA


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