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J. Electromagn. Eng. Sci > Volume 22(3); 2022 > Article
Yu and Kam: Improving Signal Integrity by Reducing Mode Conversion in Differential Pairs on a Meshed Ground in Flexible Printed Circuit Boards


Asymmetry in a differential pair leads to deterioration of signal integrity. Differential pairs on a meshed ground often encounter asymmetry in return current paths. In this paper, we propose an offset mesh as an improved mesh structure that offsets asymmetry between a solid region and an aperture region. The offset mesh mitigates the asymmetry in the conventional mesh structure without additional design elements. The proposed structure has been verified to be effective in reducing mode conversion, intra-pair and inter-pair skews, and characteristic impedance variation in the time and frequency domains. This enables high-density routing of differential pairs.

I. Introduction

The use of flexible printed circuit boards (FPCBs) in electronic devices has been increasing as these devices become thinner and smaller. Meshed ground planes have been adopted in FPCBs for impedance matching and improved flexibility [18]. Apertures of meshed ground planes cause an effective dielectric constant change and a roundabout current path that increase the inductance of the ground plane [9]. Two identical traces of a differential pair would have asymmetric return current paths on a meshed ground. This imbalance would result in mode conversion, intra-pair and inter-pair skews, increased radiated emissions, and characteristic impedance variation [1013].
To mitigate this, Hsu et al. [14] proposed the use of co-planar waveguides with a ground by adding a guard traces on both sides of the transmission line to mitigate the asymmetry in the microstrip line with a meshed ground. The guard traces replace the asymmetric return current paths in the mesh ground plane. However, the guard traces take up space that is already lacking. Wang et al. [15] proposed rotating a meshed ground by 30° rather than the conventional 45° relative to differential traces. While the impedance variation was reduced, the mode conversion did not significantly improve. Moreover, in silicon interposer, which has been actively studied recently, various design parameters in a meshed ground for impedance matching have been studied, but no new structure has been proposed [16, 17]. We introduced an offset mesh structure to alleviate the impedance variation of single-ended lines [18]. This offset mesh structure uses only the conventional top and bottom meshed ground, without additional guard traces. Therefore, this structure mitigates the imbalance that differential pairs would have without taking up additional space.
In this study, we applied the offset mesh structure to a differential pair to minimize the imbalance of the pair. There were aperture regions and a solid region with a lattice pattern in the meshed ground. Apertures of the mesh ground plane caused asymmetry. The differential pair passed the aperture region at both the top and bottom simultaneously, as shown in Fig. 1(a) and 1(b), which worsened the asymmetry between two identical traces of the differential pair. Our approach was to offset the centers of the meshes on the two layers. If a routed trace landed on top of an aperture on the top layer, it should land on a solid part of the bottom layer (or vice versa). The validity of this approach was confirmed with the results of a full 3D electromagnetic (EM) solver, the ANSYS High-Frequency Structural Simulator (HFSS) [19], CST Microwave Studio [20], circuit simulations, and Advanced Design System (ADS) software [21].

II. Configuration of the Offset Mesh

The geometry of the proposed offset mesh structure is shown in Fig. 1. The meshed ground consists of aperture regions and a solid region with a lattice pattern. Four differential pairs of eight striplines run parallel to one another between two meshed grounds. The configuration of the conventional mesh is the stripline structure with a meshed ground in Fig. 1(a) and 1(b). The configuration of the offset mesh offsets the centers of the meshes on the two layers in Fig. 1(c) and 1(d). In this way, if a routed trace lands on a solid region of the top layer, it should land on top of an aperture region on the bottom layer (or vice versa). There are mainly three variables in designing a mesh plane: (1) a trace-to-aperture intersecting angle, (2) the ratio of the aperture to the solid region, and (3) the position of the trace on the meshed plane [6].
We compared the proposed offset mesh and the conventional mesh by fixing the first two design variables. The trace-to-aperture intersecting angle of both variables, θ, was set at 45°; the size of a square aperture, b, at 1,000 μm; the edge-to-edge distance of adjacent apertures (separation), a, at 150 μm; the trace width, w, at 150 μm; the trace length, l, at 25 mm; and the trace spacing, s, at 200 μm. Eight differential ports were assigned as shown in Fig. 1, and the differential pairs 1–4 represented port 1–5, port 2–6, port 3–7, and port 4–8, respectively.

III. Results

1. Differential Insertion Loss and Characteristic Impedance Variation

To analyze the signal integrity of the differential pair, the differential-to-differential mixed-mode S-parameters, Sdd [22], were used to verify the simulation results. Fig. 2 compares the insertion loss of the differential pair on the conventional mesh with that on the offset mesh. The latter performed at least as well as the former. Moreover, the latter showed less variation in the insertion loss than the former depending on its position.
The characteristic impedance of a single-ended trace is significantly affected by the position of the trace relative to the meshed ground. While the variation in the conventional mesh was 14 Ω, the variation in the offset mesh was only 3 Ω [18].
The apertures of a meshed ground plane cause changes in inductance and capacitance [6, 9]. A roundabout current path generated by apertures increases the inductance of the ground plane. In contrast, apertures reduce the capacitance value between the trace and the ground plane. An increase in the inductance and a decrease in the capacitance of a routed trace increases the impedance. Fig. 3 shows how the characteristic impedance variation at 10 GHz changes as we move the position of a differential pair in a finer step (163 positions in one period of the conventional mesh). As shown in Fig. 3(b), when the differential pair was placed near the point where the separations intersected, it had maximum impedance. Conversely, as shown in Fig. 3(c), the section between the maximum points had the minimum impedance value. As reported in [18], using our approach, we were able to reduce the difference between the maximum and minimum impedance, and our results showed more repeated maximum and minimum impedance values, as seen in Fig. 3(a). The variations in the conventional mesh and in the offset mesh were 8.7 Ω and 4.4 Ω, respectively. The differential impedance of the two traces was less affected by the position due to the differential signaling. The return current had two paths: the ground plane and an adjacent trace of the differential pair. The proportion of the return current in each path depended on the geometry of the channel [23].

2. Mode Conversion, Intra-pair Skew, and Inter-pair Skew

To evaluate mode conversion, the differential-to-common mode-conversion amount of mixed-mode S-parameters, Scd, is generally used [22]. A trace has different effective dielectric constants depending on whether it lands on a solid region or an aperture region. Using the stripline impedance equation in [10] to obtain the effective dielectric constants in the differential mode from the impedance values in the previous section, the conventional mesh had a value of 2.1 when the impedance was the maximum and 2.6 when the impedance was the minimum. In the case of the offset mesh, the values of the aforementioned variables were 2.25 and 2.5, respectively. The estimated impact of the effective dielectric constant variation Δɛreff on the differential signaling performance was given in [24, 25]. First, the variation was related to the speed of light, c0, the frequency, ω, and the phase constant, β, as shown in Eq. (1):
Then, we verified the conversion from the differential to the common mode %CM and the phase skew Tskew using Eq. (2):
where α is the attenuation constant, z is the physical location along the transmission lines, and βV and β&Vmacr; are the phase constants for signals V and , espectively.
Fig. 4 compares the mode conversion of the two meshes. For the conventional mesh, the mode conversion was greater than −16 dB at 10 GHz in the worst case (see Scd51 or Scd84 in Fig. 4(a)). This happened when one of the two traces that consisted of a differential pair landed on a point where two separations intersected. In such a case, the two traces experienced very different effective dielectric constants, which resulted in an intra-pair skew and mode conversion. This can be greatly reduced by adopting the offset mesh. Fig. 4(b) shows that Scd51 and Scd84 were reduced by more than 10 dB. Although a differential pair was placed asymmetrically for the top mesh, this was compensated for at the bottom mesh.
Therefore, none of the four differential pairs exhibited significant mode conversion (approximately −25 dB at 10 GHz). The power sum of the common modes in the four pairs was smaller by one order of magnitude. Moreover, high-speed interconnection standards such as a USB, a display port, and HDMI had an Scd limit. It is important to meet each limit within the operating frequency range. For USB 3.1, 3.2, and 4 Gen 2, a mated cable assembly passed if the mode conversion was less than or equal to −20 dB from 100 MHz to 10 GHz [26, 27]. In the case of the mobile industry processor interface (MIPI) for D-PHY, no differential pair shall exceed −26 dB for frequencies below about 2 GHz [28]. Several of the routed buses on the conventional mesh were bound to exceed that limit, but all the routed buses on the proposed mesh met that limit due to their few changes depending on their location.
Fig. 5 shows how the extent of the mode conversion at 10 GHz changed as we moved the position of a differential pair in a finer step (48 positions in one period of the offset mesh). In the conventional mesh, a differential pair could exhibit more than −15 dB of mode conversion. However, with the proposed offset mesh, the differential pair exhibited consistently low (between −25 dB and −30 dB) mode conversion no matter where it was placed.
Figs. 6 and 7 show the transient simulation results of the intra-pair and inter-pair skews. The propagation delay, tpd, on the trace is the one-way from the source to the load time required by a signal to travel on that trace. It is a function of the dielectric constant. The difference in the propagation delay is called the skew. The skew between traces of a single differential pair is the intra-pair skew, and the skew between two or more differential pairs is the inter-pair skew. Therefore, the proposed offset mesh reduced the variation in the tpd by reducing the variation in the effective dielectrics seen on the two traces of each differential pair, as calculated by Eq. (3). Fig. 8 shows that while the conventional mesh had the worst-case intra-pair skew of 7.4 ps, that of the offset mesh was only 2.0 ps. The inter-pair skew between the differential pairs #1 and #2 in the conventional mesh was 7.4 ps. It was reduced to 3.8 ps by adopting the offset mesh in Fig. 9. The eye diagrams were simulated using a pseudorandom bit sequence (PRBS) pattern and a bit rate of 5 Gbps. The eye diagram that evaluated the differential signal integrity is shown in Fig. 10 and Table 1. The eye diagram of the offset mesh showed better eye quality than that of the conventional mesh.

IV. Conclusion

The proposed offset mesh structure enabled two striplines of a differential pair in an FPCB to have the same number of ground traces no matter where they were placed. The offset mesh was implemented without the additional design elements that are required in the conventional mesh structure. As a result, the mode conversion and the intra-pair and inter-pair skews were greatly reduced. Moreover, a uniform insertion loss was identified at any location, and the characteristic impedance variation was significantly reduced. The proposed offset mesh even showed better performance in terms of insertion loss, which gave it better signal integrity and routing flexibility.

Fig. 1
Configurations of the conventional mesh and our proposed offset mesh: (a) top view of the conventional mesh, (b) bottom view of the conventional mesh, (c) top view of our proposed offset mesh, (d) bottom view of our proposed offset mesh, and (e) side view of our proposed offset mesh.
Fig. 2
Differential insertion loss obtained using the HFSS: (a) insertion loss of the conventional mesh and (b) insertion loss of the offset mesh.
Fig. 3
Characteristic impedance changes across the positions of the differential pairs obtained using the HFSS: (a) impedance variation, (b) maximum impedance, and (c) minimum impedance.
Fig. 4
Mode conversion obtained using the HFSS: (a) mode conversion of conventional mesh and (b) mode conversion of offset mesh.
Fig. 5
Mode conversion changes across the position of the differential pair obtained using the HFSS and CST.
Fig. 6
Intra-pair skew obtained using the ADS: (a) transient simulation using a step pulse with a rise time of 100 ns to verify the conventional mesh and (b) transient simulation using a step pulse with a rise time of 100 ns to verify the offset mesh.
Fig. 7
Inter-pair skew obtained using the ADS: (a) transient simulation using a 10-GHz pulse to verify the conventional mesh and (b) transient simulation using a 10-GHz pulse to verify the offset mesh.
Fig. 8
Comparison of the intra-pair skews.
Fig. 9
Comparison of the inter-pair skews.
Fig. 10
Comparison of the simulated eye diagrams: (a) differential pair #1 in the conventional mesh and (b) differential pair #1 in the offset mesh.
Table 1
Parameters of the simulated eye diagram
Conventional Offset
Eye height (mV) 414 450
Jitter RMS (ps) 5 0
Rise time (ps) 26 16.1


1. G Pan, X Zhu, and BK Gilbert, "Analysis of transmission lines of finite thickness above a periodically perforated ground plane at oblique orientations," IEEE Transactions on Microwave Theory and Techniques, vol. 43, no. 2, pp. 383–393, 1995.
2. YL Li, EL Bradawy, EL Sharawy, L Polka, A Madrid, JC Liao, and D Figueroa, "Modeling and experimental validation of interconnects with meshed power planes," In: Proceedings of the 1997 47th Electronic Components and Technology Conference; San Jose, CA. 1997, pp 1158–1162.
3. AC Cangellaris, M Gribbons, and JL Prince, "Electrical characteristics of multichip module interconnects with perforated reference planes," IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 16, no. 1, pp. 113–118, 1993.
4. CP Chien, AF Burnett, JM Cech, and MH Tanielian, "The signal transmission characteristics of embedded microstrip transmission lines over a meshed ground plane in copper/polyimide multichip module," IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, vol. 17, no. 4, pp. 578–583, 1994.
5. J Zhao and Z Li, "FDTD analysis of the electrical performance for interconnection lines in multichip module (MCM) with perforated reference planes," IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part B, vol. 20, no. 1, pp. 34–41, 1997.
6. S Wu, H Shi, M Herndon, B Cornelius, M Halligan, and J Fan, "Modeling and analysis of a trace referenced to a meshed ground plane," In: Proceedings of 2011 IEEE International Symposium on Electromagnetic Compatibility; Long Beach, CA. 2011, pp 137–141.
7. F Xiao, K Murano, and Y Kami, "Modeling of differential line referenced to a meshed ground plane," In: Proceedings of 2014 International Symposium on Electromagnetic Compatibility; Gothenburg, Sweden. 2014, pp 735–740.
8. JG Kim, ET Lee, DH Kim, JH Lee, SY Lee, HS Kim, JS Park, and CY Cheon, "Analysis of coupling characteristics between transmission lines with a buried meshed-ground in LTCC-MCMs," In: Proceedings of the 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278); Seattle, WA. 2002, pp 825–828.

9. H Lee and J Kim, "Electrical characteristics of single and coupled stripline on meshed ground plane in high-speed package," In: Proceedings of Advances in Electronic Materials and Packaging 2001 (Cat. No.01EX506); Jeju, South Korea. 2001, pp 261–267.
10. E Bogatin, Signal and Power Integrity: Simplified. 2nd ed. Upper Saddle River, NJ: Prentice Hall, 2010.

11. J Fan, X Ye, J Kim, B Archambeault, and A Orlandi, "Signal integrity design for high-speed digital circuits: progress and directions," IEEE Transactions on Electromagnetic Compatibility, vol. 52, no. 2, pp. 392–400, 2010.
12. GH Shiue, CL Yeh, HY Liao, and PW Huang, "Significant reduction of common-mode noise in weakly coupled differential serpentine delay microstrip lines using different-layer-routing-turned traces," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 4, no. 10, pp. 1671–1683, 2014.
13. DB Lin, CP Huang, and HN Ke, "Using stepped-impedance lines for common-mode noise reduction on bended coupled transmission lines," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no. 5, pp. 757–766, 2016.
14. SKS Hsu, YC Pai, and PC Hsieh, "A novel flexible printed circuit structure for gigabit data transmission," In: Proceedings of the 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS); Taipei, Taiwan. 2012, pp 153–156.
15. C Wang, K Iokibe, and Y Toyota, "Mitigating differential skew by rotating meshed ground for high-density layout in flexible printed circuits," IEICE Electronics Express, vol. 17, no. 10, article no. 20200101, 2020. https://doi.org/10.1587/elex.17.20200101
16. K Cho, Y Kim, H Lee, J Song, J Park, S Lee, S Kim, G Park, K Son, and J Kim, "Signal integrity design and analysis of differential high-speed serial links in silicon interposer with through-silicon via," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 1, pp. 107–121, 2019.
17. K Cho, Y Kim, H Lee, H Kim, S Choi, J Song, S Kim, J Park, S Lee, and J Kim, "Signal integrity design and analysis of silicon interposer for GPU-memory channels in high-bandwidth memory interface," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 8, no. 9, pp. 1658–1671, 2018.
18. S Yu and DG Kam, "Offset mesh in FPCB for better impedance control," Electronics Letters, vol. 54, no. 13, pp. 812–813, 2018.
crossref pdf
19. HFSS, 3D electromagnetic simulation software, 2019. [Online]. Available: https://www.ansys.com/fr-fr/products/electronics/ansys-hfss

20. Dassault Systemes, CST studio suite: electromagnetic field simulation software, 2019. [Online]. Available: https://www.3ds.com/products-services/simulia/products/cst-studio-suite/?utm_source=cst.com&utm_medium=301&utm_campaign=cst

22. W Fan, A Lu, LL Wai, and BK Lok, "Mixed-mode S-parameter characterization of differential structures," In: Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003); Singapore. 2003, pp 533–537.
23. PE Fornberg, M Kanda, C Lasek, M Piket-May, and SH Hall, "The impact of a nonideal return path on differential signal integrity," IEEE Transactions on Electromagnetic Compatibility, vol. 44, no. 1, pp. 11–15, 2002.
24. H Heck, S Hall, B Horine, K Mallory, and T Wig, "Impact of FR4 dielectric non-uniformity on the performance of multi-Gb/s differential signals," In: Proceedings of the Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710); Princeton, NJ. 2003, pp 243–246.
25. H Heck, S Hall, B Horine, and T Liang, "Modeling and mitigating AC common mode conversion in multi-Gb/s differential printed circuit boards," In: Proceedings of the Electrical Performance of Electronic Packaging; Portland, OR. 2004, pp 29–32.
26. Hewlett-Packard Company, Intel Corporation, Microsoft Corporation, Renesas Corporation, ST-Ericsson, and Texas Instruments, “Universal serial bus 3.1 specifications”, 2013. [Online]. Available: https://manuais.iessanclemente.net/images/b/bc/USB_3_1_r1.0.pdf

27. USB 3.0 Promoter Group, Universal serial bus type-C cable and connector specification, 2019. [Online]. Available: https://www.usb.org/sites/default/files/USB%20Type-C%20Spec%20R2.0%20-%20August%202019.pdf

28. MIPI Alliance, MIPI Alliance Specification for D-PHY, 2009. [Online]. Available: http://www.jmrcubed.com/vr/ref_tech/mipi_d_phy_specification_v01-00-00.pdf


Seulgi Yu received his B.S. and M.S. degrees in electrical engineering from Ajou University in Suwon, Korea in 2015 and 2017, respectively. He has been pursuing a Ph.D. degree since 2017. His current research interests include signal integrity and packages for millimeter-wave applications.


Dong Gun Kam received his B.S. degree in physics with a double major in electrical engineering and his M.S. and Ph.D. degrees in electrical engineering, all from KAIST in Daejeon, Korea in 2000, 2002, and 2006, respectively. From 2007 to 2011, he worked at the IBM Watson Research Center in Yorktown Heights, NY, USA, concentrating on the subsystem design and analysis of high-speed wireline and wireless links. In 2011, he joined Ajou University in Suwon, Korea. His research interests include millimeter-wave antennas and packages and EMI/EMC. Dr. Kam is currently an associate editor of the journal, IEEE Transactions on Components, Packaging and Manufacturing Technology. He was a recipient of the 2008 DesignCon Paper Award; the 2011 Pat Goldberg Memorial Award for the best paper in CS, EE, and Math at IBM Research; and a recipient of the 2013 CPMT Outstanding Young Engineer Award.
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