Design of X-Band GaN LNA MMIC with Switched Impedance Network for Improved Noise Figure
Article information
Abstract
In this work, an X-band gallium nitride (GaN) low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) with a switched impedance network for improved noise performance is designed and fabricated using a 0.25 μm GaN WIN-semiconductor process. Notably, the term "switched impedance network" not only refers to the role of isolating receive and transmit paths, which is typically performed by a switch, but also signifies the utilization of a switch as a matching network. The size and matching loss of the proposed MMIC is minimized by replacing the LNA input-matching network with a single-pole double-throw switch. The fabricated LNA MMIC exhibits a noise figure of 1.9–2.3 dB, gain of 16–17 dB, and input/output return loss of 6–30 dB at a frequency range of 8–10 GHz. Under pulse conditions, it presents a maximum input power of 37 dBm and a saturated output power of 19 dBm.
I. Introduction
Radar technology plays a crucial role in various applications, including navigation, weather monitoring, surveillance, and military operations. Evidently, for high-performance radar systems, the quality of their components is of utmost importance. In recent years, gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) technology has emerged as a prominent choice for radar and warfare receivers owing to its excellent performance. In particular, research on high-performance microwave integrated circuits for applications with few spatial constraints is ongoing [1].
A notable characteristic of GaN low-noise amplifiers (LNAs) is their ability to withstand high input power levels compared to LNAs based on gallium arsenide (GaAs) or silicon [2–4]. Due to their wide-bandgap characteristics [5], GaN devices exhibit high breakdown voltages and power handling capabilities, making them robust in high-power environments [6]. This inherent strength against high input power enables GaN LNAs to operate without the need for additional components, such as limiters, thus simplifying the overall system design and reducing costs [7, 8]. However, it is worth noting that although GaN LNAs excel in high-power environments, a trade-off exists in terms of the noise figure (NF). GaN LNAs exhibit a higher NF than GaAs or complimentary metal-oxide-semiconductor (CMOS) LNAs, which can affect the sensitivity and performance of the receiver [9].
In this context, the integration of GaN MMIC can help compensate for insufficient NF. It enables improved overall performance and reduced assembly complexity by combining the functionalities of the transmitter and the receiver on a single chip [10]. However, one drawback of the single-chip approach is that it can be challenging to optimize the individual components to achieve the desired performance for each component. Additionally, in the case of a failure or malfunction of a specific component on the single chip, the entire chip must be replaced, thereby increasing maintenance requirements and costs. For these reasons, the front-end modules of radar systems are designed using 50 Ω LNA, switch, and power amplifier components connected via wire bonding. In this regard, an LNA–switch configuration could be a potent alternative that can strike a balance between the advantages of single-chip integration and individual-chip optimization.
The proposed structure offers a novel approach for optimizing the performance of radar systems. While a typical switch serves to isolate the transmitter and receiver paths, it also imposes losses with regard to impedance matching. However, the proposed structure enables direct matching of the switch to the optimal impedance of the LNA, consequently eliminating the requirement for additional matching networks. In addition to improving performance, it also offers the possibility of size reduction by utilizing a switch for impedance matching.
This paper presents the design and verification process of an LNA MMIC with a switched impedance matching network using a 0.25-μm GaN WIN-semiconductor process.
II. Effect of Switched Impedance Network
The conventional method for LNA input matching generally involves using lumped elements or transmission lines to transform the optimal impedance of the LNA to a standard 50 Ω. In this case, the switch does not function as a matching network and only adds to the overall loss. However, it can be used for LNA input matching to directly achieve the desired impedance matching. Since the switch enables both switching and LNA input matching through the selection of appropriate switch states, it can be referred to as a switched impedance network.
Fig. 1 shows the impedance traces of the switched impedance network and a conventional matching network, which includes a switch. The Smith chart shows that the switched impedance network contributes to minimizing the matching paths. When the switch operates as a matching network, the LNA input-matching network becomes unnecessary, thereby shortening the matching path in Fig. 1(b) to that in Fig. 1(a). In terms of loss, a significant advantage of the proposed structure is the exclusion of a series of inductors. To counter parasitic capacitance of the transistor, achieving optimal impedance matching typically requires inductors or transmission lines unless additional compensation is available. When chip size is limited, this often results in the eventual use of low Q-factor inductors. The proposed system reduces the losses associated with low Q-factor elements by removing the input matching network from the LNA. As a result of minimizing the matching paths compared to that in the conventional method and by removing the series inductor, the NF was improved due to a reduction in matching losses.
Impedance traces of (a) the switched impedance network and (b) a conventional matching network, which includes a switch.
III. Design of GaN LNA MMIC
Generally, the topology used for designing an LNA can be common-source (CS), common-gate (CG), or cascode. Among these, CS topology offers superior NF and gain performance while also being simpler [11, 12]. In fact, CS topology provides better NF performance when power is consumed in the range of a few milliamperes [13]. Therefore, the proposed GaN LNA is based on CS topology and incorporates a switch for first-stage input matching, significantly influencing overall NF performance.
To minimize NF degradation, an input matching network that uses inductive source degeneration L2 instead of a series resistor was designed. Furthermore, resistors in the kilo ohm range were used in the gate bias network to prevent performance degradation caused by high radio frequency (RF) input signals. This helps protect the transistor from a high forward gate bias owing to the RF input signals [14]. The entire mechanism is explained in Fig. 2. Notably, VGS_Q5 (=VG1 − IG · R5) reduces as the RF signal increases. This decrease in VGS_Q5 results in a decline in IG, which operates as feedback, since VG1 has a negative value. If bias resistors are not used in the gate bias, VGS_Q5 becomes positive when the RF signal exceeds VG1 due to the forward IG. In other words, the bias resistor in the gate blocks the forward IG, thus preventing VGS_Q5 from being forward-biased. Fig. 2 illustrates a schematic of the proposed X-band GaN LNA MMIC.
Schematic diagram of the proposed X-band GaN LNA MMIC.
The switched network was designed using a shunt single-pole double-throw (SPDT) switch structure. The shunt switch had low loss and facilitated LNA matching by utilizing the parasitic capacitance of the shunt transistors. Notably, Q1 and Q2 were optimized for the receive (Rx) mode, while Q3 and Q4 were optimized for the transmit (Tx) mode. Therefore, when Q1 and Q2 were turned on, the switch operated with open impedance via the transmission line, representing the switch-off state. In contrast, when Q1 and Q2 were turned off, the switch-on state was achieved, and the sizes of Q1 and Q2 were optimized for input-matching for LNA. Furthermore, the Rx mode was matched to the optimal impedance of the LNA, while the Tx mode was matched to 50 Ω. Overall, the proposed switched network maintained an asymmetric structure with different configurations for the Rx and Tx modes.
In the Rx mode, NF matching in the input impedance was determined by considering the trade-off between the input return loss and NF. When using inductive source degeneration, the maximum available gain impedance was 35.3 + j44.0 Ω at 9.5 GHz, and the minimum NF impedance was 49.0 + j16 Ω at 9.5 GHz. Consequently, the final input impedance was determined to be approximately 40.0 + j30.0 Ω, ensuring balanced performance in terms of return loss, gain, bandwidth, and NF. Fig. 3 depicts the gain, NF circles, and input-matching impedance for the first stage at 9.5 GHz. Notably, reducing the size of the transistor decreased power consumption and minimized the effect of parasitic capacitance at high frequency, resulting in superior NF performance.
Gain, noise figure circles, and input-matching impedance for the first stage at 9.5 GHz.
Additionally, it is crucial to verify whether a circuit can be unconditionally stable by implementing proper source degeneration based on transistor size. In this study, the value of the degeneration inductor was determined by accounting for changes in NF, gain circles, and matching. The sizes of Q5 and Q6 were optimized for low power consumption and better NF performance. Furthermore, the proposed switched network was designed to match the input impedance of the first stage, which usually has the most significant impact on NF characteristics. The inter-stage and output network impedances were designed primarily to achieve conjugate matching with the load and source impedances, considering the gain and return loss. Conjugate matching was achieved using a minimal number of inductors (L3, L7). Notably, a bias circuit is generally equipped with resistors and RF choke inductors (L1, L4, L5, and L6) to ensure robust operation. The resistor served to eliminate the oscillation caused by feedback loops. Furthermore, the bypass capacitors in the bias circuit restricted the influence of the connected components to the DC pad and eliminated the RF signals, which had been inadequately suppressed by the RF choke inductors.
IV. Measurement Results
Fig. 4 presents the realized GaN LNA MMIC with an integrated SPDT switch and LNA. Using the switch to match the LNA input, the chip size was minimized to 1.5 mm × 3.0 mm, including the RF and DC pads. The bare chip and printed circuit board (PCB) were attached to a jig using silver epoxy, and the DC pads of the chip were connected to the PCB through wire bonding. Subsequently, on-wafer measurements were performed by placing the probes in contact with the RF pads. The switching transistors (Q1–Q4) turned off when the gate voltage was −26 V and turned on when the gate voltage was 0 V. The first and second stages (Q5–Q6) of the LNA were biased using a drain voltage of 10 V and a gate voltage of −2.1 V, resulting in a total drain current of 25 mA.
Chip photograph of the GaN LNA MMIC.
Fig. 5 depicts the simulated and measured S-parameters in the Rx mode. The measurements exhibit a small signal gain of more than 16 dB, input return loss of more than 12 dB, output return loss of more than 6 dB, and isolation of more than 29 dB in the 7.5–10 GHz frequency range. This indicates that sufficient gain and return loss were achieved at the targeted frequency, thereby minimizing the NF degradation caused by the gain block connected to the LNA. Fig. 6 shows the simulated and measured S-parameters in the Tx mode. The measurements indicate an insertion loss of less than 0.9 dB, an input return loss of more than 12.6 dB, and an output return loss of more than 12.0 dB in the 8.0–11.2 GHz frequency range. A very low insertion loss was measured, effectively minimizing the output degradation of the power amplifier. Notably, the minor discrepancies between the S-parameter simulations and measurements point to the application of a sophisticated electromagnetic simulation setup and transistor modeling. Fig. 7 shows the simulated and measured NFs in the Rx mode. The measurements show an NF of less than 3.0 dB from 8.0 GHz to 11 GHz. Assuming that the switch loss is the same in both the Rx and Tx modes, the standalone LNA exhibited an NF of less than 2.1 dB.
Comparison between the measurement and simulation results for Rx S-parameters.
Comparison between the Tx S-parameters attained by the measurement and simulation results.
Comparison between the measurement and simulation results for noise figure.
Overall, the NF measurements exhibited a similar tendency to the NF simulations, ultimately achieving minimum NF at the targeted frequency. Fig. 8 shows the simulated and measured output powers in the Rx mode at 9.5 GHz. Output power measurements were performed under a 10% duty cycle pulse input. The output power measurements show a 1-dB compression point of 9 dBm and a saturated output power of 19 dBm. To confirm the operation of the LNA with high input power, the input power was gradually increased, even after reaching saturation. The performance of the LNA remained unaffected up to an input power of 37 dBm. Table 1 lists the performance of the previously reported GaN LNA MMICs [10, 15, 16]. Considering NF, power consumption and return loss, the proposed LNA MMIC can be regarded as a competitive one. Most importantly, the figure of merit (FoM) of the proposed X-band LNA is higher than those of the LNAs, with the FoM (W−1) measured using the following equation [13, 17]:
Comparison between the measurement and simulation results for output power in the Rx mode.
Comparison of GaN-based X-band LNA MMICs
V. Conclusion
This paper introduced an LNA MMIC with a switched impedance network to achieve size reduction and improved NF. The fabricated LNA MMIC achieved an NF of 2.6–3.0 dB, gain of 16–17 dB, and input/output return loss of 6–30 dB at the 8–10 GHz frequency range. Under pulse conditions, it exhibited a maximum input power of 37 dBm and a saturated output power of 19 dBm. Furthermore, the integrated switch allowed for the isolation of the Tx path, with the insertion loss of the Tx mode being 0.7–0.9 dB at the 8.0 GHz–11.2 GHz frequency range. It is anticipated that since the proposed design serves as a balance between the single-chip frontend and individual chips, it can be considered an alternative to both.
Notes
This work was supported by a grant-in-aid from Korea Research Institute for defense Technology planning and advancement (KRIT) through the Weapon Systems Parts Localization R&D program (No. C210042).
References
Biography
Byeong-Uk Lee, https://orcid.org/0000-0002-4041-764X received his B.S. and M.S. degrees in electronic engineering from Hankuk University of Foreign Studies, Yongin, Korea, in 2016 and 2018, respectively. He is currently an engineer at Hanwha Systems. His research interests include GaAs- and GaN-based MMICs and radar system design.