A 6.1-to-41.5 GHz CMOS Low-Noise Amplifier for Wideband and Highly Linear Applications

Yeheon Park; Kyeonghun Choe; Sanggeun Jeon

doi:10.26866/jees.2025.2.r.287

J. Electromagn. Eng. Sci > Volume 25(2); 2025 > Article

Park, Choe, and Jeon: A 6.1-to-41.5 GHz CMOS Low-Noise Amplifier for Wideband and Highly Linear Applications

Regular Paper

Journal of Electromagnetic Engineering and Science 2025;25(2):154-159.

Published online: March 31, 2025

DOI: https://doi.org/10.26866/jees.2025.2.r.287

A 6.1-to-41.5 GHz CMOS Low-Noise Amplifier for Wideband and Highly Linear Applications

Yeheon Park

, Kyeonghun Choe

, Sanggeun Jeon^*

School of Electrical Engineering, Korea University, Seoul, Korea

^*Corresponding Author: Sanggeun Jeon (e-mail: sgjeon@korea.ac.kr)

Received January 2, 2024 Revised May 14, 2024 Accepted June 27, 2024

This is an Open-Access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/4.0) which permits unrestricted non-commercial use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper presents a CMOS low-noise amplifier (LNA) for wideband applications that require high linearity. A frequency staggering technique is employed to achieve a flat gain response over a wide frequency band. In the first stage, the LNA uses a common-source topology with resistive feedback to achieve wideband input matching, while inductive series peaking is adopted at the output to attain gain peaking at a high frequency. In the second stage, an inductive load with high inductance is employed to ensure low-frequency gain and high linearity. Furthermore, the bias condition of the transistors is optimized by considering the trade-off between linearity and DC power consumption. The proposed LNA achieved a measured peak gain of 10.5 dB at 18 GHz and a wide 3-dB bandwidth ranging from 6.1 to 41.5 GHz. The third-order intercept point exceeded 1.3 dBm, and the input matching remained below −8 dB over the entire 3-dB bandwidth. Furthermore, the noise figure ranged from 4.7 to 7.3 dB up to 26.5 GHz.

Keywords: High Linearity Input Matching, LNA, Resistive Feedback, Wideband

I. Introduction

A wideband low-noise amplifier (LNA) is employed in various applications, ranging from multiband communication receivers to measurement instruments [1–3]. For instance, a CMOS integrated vector network analyzer requires a wideband LNA to receive the reference and reflected signals of devices under test at wideband frequencies [1].

However, designing a wideband LNA for millimeter wave (mm-wave) frequencies is a challenging task because of the obvious trade-off between wideband impedance matching and achieving a low noise figure. Several approaches have been pursued to overcome this trade-off [4–6]. LC-based matching and resistive feedback techniques are commonly used for wideband matching [4]. Furthermore, the inductive peaking technique offers a good balance between gain, noise figure, and bandwidth [5]. In [6], the complementary common-gate (CG) and common-source (CS) stages were cascaded to achieve wideband operations. However, the parasitic elements of the PMOS transistors imposed limitations on the overall bandwidth of the amplifier.

In addition, multiple bandwidth extension techniques, including feedback and shunt-series peaking [7], as well as distributed amplifier structures [8], have been proposed for wideband impedance matching. However, these methods involve significant DC power consumption (P_DC) and require a large chip area. Furthermore, while self-biased resistive feedback topologies [9], [10] allow wideband operations, they also use resistive loads, which degrade linearity performance. In this work, we propose a wideband LNA that employs resistive feedback and series inductive peaking techniques to achieve high linearity and good input matching over a wide bandwidth.

II. Design of Wideband and Highly Linear LNA

Fig. 1 presents a schematic of the proposed wideband LNA with high linearity. Two CS stages were cascaded to ensure sufficient gain. Moreover, to achieve a flat gain over wideband frequencies, the frequency staggering technique was employed. In the first CS stage, resistive feedback (R_f) and inductive source degeneration (L_s) were employed for wideband input matching and to achieve a low noise figure. The R_f also provided self-biasing to M₁. By introducing inductive series peaking (L₁), the gain in the first stage was enhanced at high frequencies, resulting in a high-pass response within the operating frequency band of interest, as shown in Fig. 2. Notably, it was observed that the low-frequency power gain declined in the first stage due to the input capacitance of the following stage.

The second stage of the LNA employed an inductive load (L_d) instead of a resistive load. The value of L_d was intentionally chosen to be quite high (= 1.2 nH) so that it resonates with the parasitic capacitance at a low frequency, thus boosting the low-frequency gain. Fig. 2 shows that the first stage achieved its peak gain at 37.6 GHz, whereas the second stage did so at 5.9 GHz. By combining these two different frequency responses, the LNA achieved a flat gain over a wide frequency range.

1. Wideband Input Matching with Resistive Feedback

Fig. 3 depicts an equivalent circuit for the input matching network. For simplicity, transistor M₁ was modeled using gate-to-source capacitance (C_gs) and transconductance (g_m).

The load impedance of M₁ was solely assumed to be R_d, disregarding C₁ and L₁. This is because L₁ would resonate with the parasitic capacitance at the drain nodes of M₁ and C₁, resulting in high impedance at the operating frequency. The input impedance (Z_in) of the LNA can be expressed as follows [10]:

(1)

Zin=Zfb//Zg,

(2)

Zfb≈(Rd+Rf)(1-ω2Cgs[Lg+Ls])gmRd+jω(Rd+Rf)RdLs,

(3)

Zg=jω(Lg+Ls)+1jωCgs+gmCgsLs.

Here, Z_in refers to a parallel combination of feedback impedance (Z_fb) and gate impedance (Z_g). At low frequencies, the magnitude of Z_g was found to be significantly higher than that of Z_fb. Consequently, Z_in was primarily determined by Z_fb, while Z_g was neglected. This led to Z_in being approximated as (R_d+R_f)/g_mR_d. Therefore, to achieve the initial design target of an input reflection coefficient of −10 dB, Z_in was chosen as 94 Ω. This resulted in R_f being 200 Ω under conditions of R_d = 40 Ω and g_m = 63 mS.

As the frequency increased, the reactive components of Z_fb and Z_g became non-negligible. Therefore, to resonate out the reactive components, source degeneration inductance (L_s) and gate inductance (L_g) were added to match Z_in to 50 Ω.

Fig. 4 depicts the results obtained by comparing the input matching and gain performance of two cases, where one case involves the use of only R_f while the other uses both R_f and the two inductances (L_s and L_g). It is observed that L_s and L_g significantly improved the input matching performance (|S₁₁|) at high frequencies while having minimal effect at low frequencies. Furthermore, the gain (|S₂₁|) is slightly enhanced by the inductances to reach up to 39 GHz.

2. Design for High Linearity

Since the last transistor stage usually dominates the linearity of a cascaded amplifier [11], the second CS stage of the LNA was designed with a focus on linearity. In contrast to the first stage, in which a resistive load was employed for low-frequency gain, an inductive load (L_d) was used in the second stage. The L_d not only compensated for the gain drop caused by parasitic capacitances at high frequencies but also secured a larger voltage headroom compared to the resistive load, thus improving linearity.

Linearity is also influenced by transconductance (g_m), the gate-to-drain capacitance (C_gd) of transistors, and source degeneration impedance (L_s) [12]. Among these, an increase in g_m significantly reduces third-order harmonic distortion. Notably, g_m can be increased by increasing the transistor size and overdrive voltage (V_ov =V_gs–V_th, where V_gs and V_th are the gate-to-source voltage and threshold voltage, respectively) while keeping the drain voltage fixed. In this study, the gate width (W) of the second stage was determined to be 40 μm. Furthermore, the overdrive voltage was tuned for linearity by controlling V_gs.

With a rise in V_ov, g_m increased, thus improving linearity but also increasing the P_DC. Therefore, to ensure a fair comparison that accounts for the trade-offs among linearity, P_DC, and gain, a performance parameter of Gain × (IIP₃/P_DC) was considered, with IIP₃ being the input third-order intercept point. Fig. 5 plots the performance parameter of a transistor with W = 40 μm and V_d = 1.2 V at different values of V_gs. It is observed that the transistor performance parameter continued to decrease with an increase in V_gs. Nonetheless, V_gs of 0.5 and 0.6 V resulted in a very low gain of less than 10 dB, due to which they were not chosen. Instead, V_gs of 0.7 V was chosen to ensure optimum operation in terms of the gain, linearity, and P_DC. Furthermore, it is observed that the transistor performance parameter exhibits a relatively flat response over a wide frequency band up to 45 GHz at V_gs = 0.7 V.

III. Measurement Results

The wideband and highly linear LNA was fabricated using 28-nm CMOS technology. Fig. 6 presents a chip photograph of the LNA, including all the probing pads, occupying an area of 0.65 mm × 0.56 mm. The DC power consumption was set to 25.2 mW at a drain bias of 1.2 V.

Fig. 7 shows the measured S-parameters and noise figure of the LNA. The peak gain achieved was 10.5 dB at 18 GHz. Furthermore, the 3-dB gain bandwidth was 35.4 GHz, covering a frequency range from 6.1 to 41.5 GHz. This corresponds to a fractional bandwidth as wide as 149%. The input matching (|S₁₁|) was less than −8 dB over the entire 3-dB bandwidth. Notably, the output of the LNA was not necessarily matched to 50 Ω because it usually drives a subsequent mixer that presents a capacitive load [13]. The noise figure, ranging from 4.7 to 7.3 dB, was measured only up to 26.5 GHz due to a lack of equipment. Notably, in the simulation, the noise figure ranged from 5.0 to 7.0 dB for 6.1 to 41.5 GHz. Overall, the measured S-parameters and noise figures agreed well with the simulation.

Fig. 8 presents the measured IIP₃ with 10 MHz tone spacing. It is observed that IIP₃ is 3 dBm at 16.1 GHz, and is higher than 1.3 dBm over the entire 3-dB bandwidth.

In Table 1, the performance of the LNA proposed in this work is summarized and compared to that of previously reported mm-wave wideband LNAs with a bandwidth exceeding 20 GHz [4, 10, 14–17]. The proposed LNA achieved the highest IIP₃ while also presenting a wide 3-dB bandwidth of 35.4 GHz. Furthermore, a figure-of-merit (FoM) was defined to evaluate the overall performance of the LNAs as follows [14]:

(4)

FoM=Peak gain[lin.]·3dB BW[GHz]·IIP3[mW](Noise figure[lin.]-1)·Chip size[mm2]·PDC[mW].

Owing to its optimized design in terms of gain, bandwidth, linearity, and P_DC, the LNA proposed in this work was able to achieve a competitive FoM.

IV. Conclusion

In this research, an mm-wave wideband LNA characterized by high linearity, fabricated on 28-nm CMOS technology, is proposed. Resistive feedback along with inductive source degeneration was employed in the first transistor stage to achieve wideband input matching. To attain high linearity, an inductive load was used in the second stage. Furthermore, the gate bias condition was optimized based on a trade-off between the gain, linearity, and P_DC. The proposed LNA exhibited a wide 3-dB bandwidth ranging from 6.1 to 41.5 GHz, along with a peak gain of 10.5 dB and the lowest noise figure being 4.7 dB. Its IIP₃ was measured to be 3 dBm at 16.1 GHz. Therefore, the proposed LNA can be considered suitable for use in wideband and highly linear applications in the mm-wave frequency band.

Notes

This work was supported by the IITP (Institute of Information & Communications Technology Planning & Evaluation)-ITRC (Information Technology Research Center) grant funded by the Korea government (Ministry of Science and ICT) (No. IITP-2025-RS-2020-II201749).

Fig. 1

Schematic of the wideband LNA with high linearity.

Fig. 2

Gain characteristics of the individual stages and the overall LNA.

Fig. 3

Equivalent circuit model for the input matching network.

Fig. 4

Simulated input matching and gain considering only R_f (dashed line) and R_f, L_s, and L_g (solid line).

Fig. 5

Transistor performance parameter of Gain × (IIP₃/P_DC) at different values of V_gs.

Fig. 6

Chip photograph of the LNA.

Fig. 7

Measured S-parameters and noise figure.

Fig. 8

Measured IIP₃ with 10 MHz tone spacing at 16.1 GHz.

Table 1

Performance summary and comparison of mm-wave wideband LNAs

Study	Technology	Peak gain (dB)	3-dB BW (GHz)	Noise figure (dB)	IIP₃ @freq (dBm @GHz)	P_DC (mW)	Chip size (mm²)	FoM
Chen et al. [4]	0.18 μm CMOS	16.6	7.2–27.3	3.3–3.72	−5.5 @24	13.2	0.32	7.97
Feng et al. [10]	65 nm CMOS	11.5	2.1–39.0	4.5–6.5	−5.7 @N/A	25.5	0.16	5.03
Chen et al. [14]	65 nm CMOS	13.5	19.2–42.6	3.1–4.5	−3 @22	6.36	0.26	32.20
Chang et al. [15]	65 nm CMOS	20.1	17.7–42.9	3.6	−15 @28	18	0.40	0.86
Dong et al. [16]	55 nm CMOS	20.3	0.4–30.0	2.5–4.3	−15.9 @N/A	23.5	0.39	1.10
Wang et al. [17]	65 nm CMOS	19.5	18–44	2.6–3.5	−23 @20	17	0.16	0.55
This work	28 nm CMOS	10.5	6.1–41.5	4.7–7.3	3 @16.1	25.2	0.36	13.37

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Biography

Yeheon Park, https://orcid.org/0009-0007-6334-9524 received his B.S. degree in Electrical engineering from Chungbuk National University, Cheongju, Korea, in 2022, and his M.S. degree in Electrical engineering from Korea University, Seoul, Korea, in 2024. He is now with Samsung Electronics Company. His research interest lies in millimeter-wave wideband applications.

Biography

Kyeonghun Choe, https://orcid.org/0000-0002-2106-0796 received his B.S. degree in Electrical engineering from Ulsan University, Ulsan, Korea, in 2023 and his M.S. degree in Electrical engineering from Korea University, Seoul, Korea, in 2025. He is now with SK Hynix. His current research interests include integrated circuits and waveguide package design.

Biography

Sanggeun Jeon, https://orcid.org/0000-0001-7453-2331 received his B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, South Korea, in 1997 and 1999, respectively, and his M.S. and Ph.D. degrees in electrical engineering from the California Institute of Technology (Caltech), Pasadena, CA, USA, in 2004 and 2006, respectively. From 1999 to 2002, he worked as a full-time instructor in electronics engineering for the Korea Air Force Academy, Cheongwon, South Korea. From 2006 to 2008, he was a research engineer with the Caltech High-Speed Integrated Circuits Group. Since 2008, he has been with the School of Electrical Engineering, Korea University, Seoul. His research interests include integrated circuits and systems at microwave, millimeter-wave, and terahertz bands for high-speed wireless communication and high-resolution imaging applications.