Introduction
A gallium nitride (GaN) high electron mobility transistor (HEMT) has high power density, high thermal conductivity, high breakdown voltage, and high electron mobility. Therefore, it is widely used in RF power amplifier transmitters for active electronically scanned array radars and cellular base stations [1–3].
To design and evaluate a GaN HEMT power amplifier, a large-signal model that accurately describes the nonlinear characteristics of the transistor is required. In most cases, it is preferable to extract an accurate large-signal model for a small-sized transistor from on-wafer measurements and scale it up for a large-sized transistor [4–8].
Under typical bias conditions, a large-sized transistor dissipates high power, which causes the internal channel temperature to rise and leads to self-heating [9]. For a large-sized GaN HEMT, the channel temperature rises as the number of gate fingers in the transistor increases. It is also affected by the thickness of the package substrate used for the transistor. Typically, the thicker the package substrate, the greater the increase in the channel temperature. Furthermore, the channel temperature increase affects the accuracy of the large-signal transistor model.
The present study analyzed the channel temperatures of GaN HEMTs with different numbers of gate fingers and package thicknesses using a three-dimensional finite element method (FEM) of Ansys Fluent software. The simulation results showed that channel temperature depended not only on the GaN HEMT structure but also on the number of gate fingers and the package thickness.
Since channel temperature influences the output power characteristics of GaN HEMTs, we considered the thickness of the package substrate to obtain a more accurate large-signal model for a 140-W GaN HEMT. Since a unit transistor has 10 gate fingers, and the large-signal model of the 140-W GaN HEMT has 8 unit transistor models in parallel, this model has 80 gate fingers. The unit transistor model can be obtained using AM-CAD’s IVCAD commercial software and Keysight’s PNA-X test equipment [3, 10, 11].
The channel temperatures of the unit transistor and the high-power transistor were simulated and measured, and package thickness was taken into account. The accuracy of the model was improved by examining the thermal resistance effects of transistor size and package thickness, and was validated using load pull simulation and measurement.
Thermal Analysis of Packaged GaN HEMTs
To develop a high-power GaN HEMT, a unit transistor with a small number of gate fingers is developed and verified, and then unit transistors are combined in parallel. The development process for a large-signal transistor model is similar. A large-signal model of a unit transistor is developed, and then a high-power transistor model is made by connecting unit transistor models in parallel.
Fig. 1 shows photographs of GaN HEMTs fabricated by using the Wavice baseline process for 0.4 μm GaN HEMT [12]. Fig. 1(a) shows a 10-finger unit transistor (GaN HEMT) attached to a package substrate for model extraction and on-wafer load pull measurement, and Fig. 1(b) shows a unit transistor with 10 gate fingers and a high-power transistor with 80 gate fingers attached to package substrates for measurement in a test fixture.
The total gate peripheries of the unit and high-power transistors were 3.5 mm and 28 mm, respectively. The package substrate was a CPC141 material, and an Au/Sn (80:20) alloy was used for eutectic bonding. The package sizes for the unit and high-power transistors shown in Fig. 1(b) were 4.07×13.97×1.4 mm3 and 5.8×20.3×1.4 mm3, respectively.
Fig. 2 shows infrared (IR) images of the unit transistor with 10 gate fingers under normal bias conditions of VDS = 50 V and IDS = 0.12 A and the high-power transistor with 80 gate fingers under normal bias conditions of VDS = 50 V and IDS = 0.96 A. The bias conditions were set to ensure that each gate finger dissipated the same power (0.6 W). A Quantum Focus Instruments (QFI) InfraScope was used to measure the IR images of the transistors. The dissipation power density for each transistor was 1.71 W/mm. At the base plate temperature condition of 90°C, the maximum temperatures of the unit and high-power transistors were 131.5°C and 189.4°C, respectively.
Channel temperature is a key parameter affecting the electrical performance and reliability of a high-power transistor. Since a GaN HEMT with 80 gate fingers consists of 8 unit transistors and has different channel temperatures over the position, its large-signal model should include position-dependent temperature effects to accurately describe its electrical and thermal behaviors.
We investigated the thermal effects of the number of gate fingers and package thickness on the high-power transistor’s channel temperature and improved the large-signal model by adding power-dependent constant and tapered thermal resistance to each unit transistor.
Fig. 3 depicts a GaN HEMT structure for the thermal FEM simulation using Ansys Fluent software in which a gate finger with gate length LG and gate width WG was a heat source in the simulation. In this figure, tG, tS, and tD represent the thickness of a GaN layer, a silicon carbide (SiC) substrate and a package substrate, respectively. The sizes of the transistor and the package substrate were a × b and A × B, respectively. Regarding boundary conditions, the bottom of the package substrate was set to a constant temperature of 26.85°C and the other surfaces of the structure were assumed to be adiabatic walls.
The geometric parameters used for the thermal simulation are listed in Table 1. The thermal conductivity of GaN, SiC, and the package substrate were calculated as follows:
The dissipated power at each gate finger was set to 0.2 W. The geometrical parameter b of the transistor structure in Fig. 3 was 800 μm for the 10-finger GaN HEMT, and it increased as the number of gate fingers increased. Since the transistor was symmetrical, the thermal simulation was performed for half of the structure.
Fig. 4 shows the simulated three-dimensional temperature distributions for the 10-finger, 20-finger, 40-finger, and 80-finger transistors with tD = 1,400 μm. Fig. 5 depicts the temperature distributions along the centers of the transistor structures. The temperature difference ΔT between the 10-finger and 80-finger transistors was 12.45°C. The same thermal simulation was conducted for a substrate thickness of tD = 100 μm.
Fig. 6 shows the simulated temperature distributions for the 10-finger, 20-finger, 40-finger, and 80-finger transistors with tD = 100 μm. Fig. 7 depicts the temperature distributions along the centers of the transistor structures. The temperature difference ΔT between the 10-finger and 80-finger transistors was 1.65°C.
The thickness of the package substrate also plays an important role in determining the channel temperature of multigate GaN HEMTs. Therefore, a similar thermal simulation was performed for variations in substrate thickness under a dissipation power condition of 0.1 W per gate finger. Fig. 8 plots the maximum channel temperatures against the number of gate fingers for the substrate thickness (tD) of 0–3 mm.
Fig. 9 shows the maximum channel temperatures of a GaN HEMT in which gate length LG, gate width WG, gate spacing s, boundary spacing L, and GaN thickness tG had values that differed from the default values listed in Table 1. The thermal simulation was performed for substrate thickness (tD) values of 0 mm and 1 mm under a dissipation power condition of 0.1 W per gate finger.
Figs. 8 and 9 show that thinner package substrates led to lower maximum temperatures and that temperature change was insensitive to changes in other geometrical parameter values. Therefore, the contribution of the package substrate to the heat transfer characteristics was fully considered in developing a large-signal model of a high-power GaN HEMT.
Large Signal Model of the 80-Finger GaN HEMT
This section shows that the large-signal model of a GaN HEMT can be improved by including the thermal effect of the package substrate.
1. Channel Temperature of the 140-W GaN HEMT
Fig. 10 presents the measurement setup for the IR images of GaN HEMTs in Fig. 2. The package type shown in Fig. 1(b) was used for the IR image measurement of a unit transistor.
For convenience, an internal matching circuit was applied to the package substrate to measure the 80-finger GaN HEMT. In the measurement, no RF signal was applied, and only DC bias voltages were used.
A thermal chuck and a thermocouple were used to keep the base plate of the package at a constant temperature. The magnification of the lens of the IR camera was 2× for the unit transistor and 5× for the high-power transistor.
Fig. 11 shows the channel temperature distributions along the longitudinal center lines of the unit and high-power transistors obtained from the IR images in Fig. 2. The channel temperatures of these transistors were also simulated using Ansys Fluent software. The geometric parameters of the transistors for the thermal simulation are listed in Table 2. The tB parameter was added for an eutectic bonding layer between the transistor and the package substrate.
The following thermal conductivity values were used for the bonding material and the package substrate:
The temperature-dependent and nonlinear thermal conductivity of GaN and SiC [13] were calculated as follows:
where T is in kelvin.
The thermal conductivity of a copper jig was included in the thermal simulation as kCu = 398 W/mK and the thickness and dimensions of the copper jig were 5 mm and 45×60 mm2, respectively, for the 10-finger GaN HEMT and 10 mm and 62×88 mm2, respectively, for the 80-finger GaN HEMT. For the simulation boundary conditions, the jig bottom surface was set at a constant temperature of 90°C, and other surfaces were assumed to be adiabatic walls.
The gate finger with gate length LG = 0.4 μm and gate width WG = 350 μm was assumed to be a heat source. The dissipation power density per transistor was 1.71 W/mm; this was the same value as the one in the IR image measurement setup.
The channel temperature distributions along the longitudinal center lines of the 10-finger and 80-finger GaN HEMTs were obtained from the Ansys Fluent thermal simulation and are given in Fig. 12. As shown in Figs. 11 and 12, the channel temperatures of the gate fingers on the edge of the gate finger array were lower than those in the center area. Furthermore, the channel temperatures of the gate fingers in the 10-finger transistor were lower than those in the 80-finger transistor. These results indicate that different numbers of gate fingers in the gate array can lead to different channel temperatures and thermal behaviors even under the same dissipation power condition.
2. Thermal Resistance Scaling
Fig. 13(a) shows an image of an 80-finger GaN HEMT fabricated using the Wavice [12] baseline process for a 0.4 μm GaN HEMT, and Fig. 13(b) depicts its equivalent circuit model. The 80-finger transistor consisted of 8 unit transistors, and its equivalent model was made by connecting equivalent models of the unit transistors in parallel.
Differences in the channel temperatures of GaN HEMTs can cause reliability problems and performance degradation. Therefore, since the large-signal model of the 80-finger transistor consists of 8 10-finger large-signal models in parallel, it should include temperature effects for improved accuracy.
Thermal resistance, which represented the channel temperature in the large-signal model of the GaN HEMT, was obtained as follows:
where Tch and Tamb are channel temperature and ambient temperature, and Pdiss is the dissipation power in the transistor.
Channel temperatures should be accurately measured for the large-signal modeling of the transistor. IR thermography is a well-known optical temperature measurement technique that gives the temperature distribution all over the transistor [14]. The maximum temperature value was used to calculate the thermal resistance related to the transistor. Electrothermal methods based on temperature-sensitive electrical parameters, such as drain saturation current IDSS or on-resistance RON, calculate the average channel temperatures of transistors and are used in most cases of large-signal modeling of small-sized transistors.
Thermal resistance is used as a representation of average channel temperature in the compact large-signal model of the GaN HEMT [15, 16]. To consider the channel temperature increment, the thermal resistance of each unit transistor was modified in the equivalent circuit model of the high-power transistor.
The thermal resistance of the unit transistor used in the high-power transistor was expressed as follows:
where Rth0 is the thermal resistance of the unit transistor measured by the electrothermal method, ΔTmax_L is the difference between the maximum channel temperature of the high-power transistor and the ambient temperature, and ΔTmax_0 is the difference between the maximum channel temperature of the unit transistor and the ambient temperature. ΔTmax_L and ΔTmax_0 can be simulated or measured using several methods [15–17]. The thermal resistance Rth0 of the unit transistor can be measured using the electrothermal method during the parameter extraction of the large-signal model. One study [3] applied the electrothermal method by using pulsed IV characteristics proposed by Joh et al. [17] in the large-signal modeling of the unit transistor. The measured thermal resistance Rth0 of the unit transistor in Fig. 13 was 3.75°C/W [3].
For the thermal resistance calculation, the channel temperatures of the transistors attached to the package substrates shown in Fig. 1(a) and 1(b) were simulated using Ansys Fluent software. The geometric parameters of the transistors for the thermal simulation are listed in Table 3.
As a boundary condition, the bottom surface of the package substrate was set at a constant temperature of 25°C, which was the environment temperature for the model extraction and load pull measurement of the transistors. The dissipation power density was 1.71 W/mm per transistor. The temperature differences were ΔTmax_0 = 48.73°C for the unit transistor and ΔTmax_L = 78.32°C for the 80-finger transistor.
The modified thermal resistance of the unit transistors used in the high-power transistor model was calculated as Rth0_L = 1.61 × Rth0 = 6.04°C/W from Eq. (10). Fig. 14(a) and 14(b) show the respective thermal simulation results for the unit transistor (Fig. 1(a)) and the 80-finger high-power transistor (Fig. 1(b)) attached to the package substrates.
3. Thermal Resistance Tapering
Rth0 was the average thermal resistance of the unit transistor only, and Rth0_L was the average thermal resistance of the unit transistors used in the high-power transistor. The high-power transistor was much larger than the unit transistor, and the temperature distribution of the high-power transistor was greater than that of the unit transistor. Therefore, we considered thermal resistance tapering for the unit transistors in the high-power transistor by applying Eq. (10) to each unit transistor in the high-power transistor. We compared the maximum temperature difference ΔTmax_i_L of i-th unit transistor with the maximum temperature difference ΔTmax_0 of the unit transistor only. We derived the thermal resistance of each unit transistor in the high-power transistor from the thermal simulation results shown in Fig. 14 as follows:
where Rthi is the thermal resistance of the i-th unit transistor in the high-power transistor shown in Fig. 13.
4. Validation of the High-Power Transistor Model
The large-signal model of the high-power transistor had three types of thermal resistance for the unit transistor. The first was directly obtained using the electrothermal method during the large-signal modeling process of the unit transistor, the second was the scaled average thermal resistance obtained from the comparison of the temperature difference between the transistors, and the third was the tapered thermal resistance. The largesignal model for the unit transistor was obtained using AM-CAD’s IVCAD commercial software [3, 10, 11].
The load pull simulation was performed using Keysight’s Advanced Design System (ADS) to validate the proposed largesignal model of the 140-W GaN HEMT. The load pull for the 80-finger high-power transistor was simulated using the three types of thermal resistance. Fig. 15 compares these results as well as the load pull results measured using Maury Microwave’s MT1000. The high-power transistor was biased at VDS = 40 V, VGS = −2.6 V, and IDS = 11 mA, and it was pulse modulated at 3.2 GHz with a 30-μs pulse width and a 3.4% duty cycle. A constant ambient temperature of 25°C was maintained.
In Fig. 15, the solid lines represent the Pout contours, and the dashed lines represent the power-added efficiency (PAE) contours. The purple solid and dashed lines indicate the results simulated using Rth0_L = 3.75°C/W. The blue solid and dashed lines indicate the results simulated using the scaled thermal resistance of Rth0_L = 1.61 × Rth0 = 6.04°C/W. The light blue solid and dashed lines indicate the results simulated using the tapered thermal resistance of Eq. (11). The steps of the Pout contours and the PAE contours were 0.5 dB and 5%, respectively.
The reference impedance planes on the input and output ports were at the edge of the package substrate; the reference planes are same as those in [3]. Table 4 shows the power characteristics of the 80-finger high-power transistor at the impedances for maximum output power and maximum PAE.
The load pull results for the 80-finger transistor simulated using the three types of thermal resistance were compared with the measured results. The load pull results simulated using scaled thermal resistance and tapered thermal resistance were more consistent with the measured results than the results using constant thermal resistance of the unit transistor.
Figs. 16 and 17 present the power gain and PAE of the 80-finger high-power transistor at the load impedance condition for maximum output power. The simulated and measured power performance results showed that the large-signal models with scaled thermal resistance and tapered thermal resistance yielded more accurate results for the 80-finger transistor than the results using constant thermal resistance of the unit transistor.
Conclusion
In this study, we proposed a method to improve the accuracy of the large-signal model of a high-power GaN HEMT by considering the thermal effects of the package substrate. The thermal analysis of various package substrates showed that substrate thickness led to an increase in channel temperature as the number of gate fingers increased. Furthermore, we showed that, to develop an accurate large-signal model of a high-power multi- finger GaN HEMT, the channel temperature difference between the high-power transistor and the unit transistor owing to the package substrate thickness should be carefully considered. Moreover, we improved the accuracy of the large-signal model of the 140-W 80-finger GaN HEMT by modifying the thermal resistance of the unit transistors used in the model according to the channel temperature difference of the unit transistors.
PDF Links
PubReader
ePub Link
Full text via DOI
Download Citation
Print
