A D-Band Hybrid-Type CMOS Phase Shifter with Full 360° Phase Coverage

Article information

J. Electromagn. Eng. Sci. 2025;25(4):391-393

Publication date (electronic) : 2025 July 31

doi : https://doi.org/10.26866/jees.2025.4.l.27

Eunjung Kim ^a

, Sanggeun Jeon ^b

School of Electrical Engineering, Korea University, Seoul, Korea

^*Corresponding Author: Sanggeun Jeon (e-mail: sgjeon@korea.ac.kr)

ahttps://orcid.org/0009-0003-4832-5250

bhttps://orcid.org/0000-0001-7453-2331

Received 2024 April 11; Revised 2024 September 9; Accepted 2024 December 2.

Abstract

This paper presents a D-band phase shifter fabricated using 65-nm CMOS technology that provides continuous full 360° phase shift. To achieve moderate insertion loss with low DC power, a hybrid-type topology is adopted by combining a 180° reflection-type phase shifter (RTPS) and an active phase inverter (PI). For the reflective load of the RTPS, a pi-type structure with an L-section matching network is employed to achieve a sufficient phase shift range and minimize insertion loss variation. Meanwhile, for the PI, a Gilbert cell structure is adopted to reduce the amplitude and phase error, while transistor sizes are optimized for minimal DC power consumption. The proposed phase shifter exhibits a measured peak gain of −12.1 dB at 147.2 GHz, along with a continuous 360° phase shift. The 3-dB bandwidth is found to be 17.5 GHz within the 136.2 GHz to 153.7 GHz range, within which the RMS amplitude error is maintained below 2 dB, while DC power consumption is only 12 mW.

Keywords: CMOS; D-Band; Phase Shifter; Phase Inverter (PI); Reflection-Type Phase Shifter (RTPS)

I. Introduction

The D-band (110–170 GHz) spectrum holds promise for various applications, such as high-resolution imaging and high-speed wireless communication. However, it necessitates the implementation of beamforming and phased-array techniques to overcome high free-space path loss and atmospheric absorption.

In this context, a phase shifter is an essential circuit block that controls each channel of a phased-array system. Several phase shifters have been proposed for use in the D-band [1–8]. For instance, active vector modulator phase shifters (VMPSs) are widely used due to their potential for high gain and 360° phase shifting capability. However, most of them fail to provide gain due to their limited transistor speed or passive loss in the D-band, while also consuming significant DC power. In contrast, passive phase shifters, such as reflection-type (RTPS) or switched-line-type (STPS) shifters, offer the advantage of zero power consumption but suffer from high insertion loss and a limited phase shift range. In particular, STPSs operate as digital phase shifters but offer limited phase resolution.

This paper presents a full 360° phase shifter in the D-band. By adopting a hybrid-type topology based on RTPS and an active phase inverter (PI), a continuous phase shift of 360° is achieved along with moderate insertion loss while consuming low DC power.

II. Circuit Design

Fig. 1 presents the schematic of the proposed D-band phase shifter. The 360° phase shifter is composed of an RTPS and a PI, which provide continuous 180° phase shift and 0°/180° phase inversion, respectively.

Fig. 1

(a) Schematic and (b) chip photograph of the proposed phase shifter.

The RTPS consists of a 90° hybrid coupler and a reflective load. The 90° hybrid coupler adopts a transformer-based structure to maintain a compact size. The reflective load assumes a pi-type structure consisting of two varactors controlled by V_ctrl and an inductor (TL₂) to ensure a sufficient phase shift range of more than 180°. Furthermore, an L-section matching network (TL₁ and C₁) is added between the 90° coupler and the reflective load to minimize insertion loss variation across the different phase states of the RTPS.

Fig. 1 also demonstrates that a Gilbert cell structure is employed for the PI to mitigate amplitude variation and phase error. To improve the gain, a high impedance line (TL₄, Z₀ = 78 Ω) is added between the common-source (M₃ and M₄) and common-gate (M₅ – M₈) stages of the Gilbert cell. Additionally, to minimize DC power consumption, all transistors comprising the Gilbert cell are used in a small size of 4 μm × 0.06 μm. As a result, the PI consumed only 12 mW at the expense of a decrease in gain. Transformers and transmission lines are employed at the input and output of the PI for impedance matching and to enable easy connection with the RTPS.

III. Measurement Results

The proposed D-band phase shifter was fabricated using 65-nm CMOS technology. The chip micrograph is shown in Fig. 1(b). The chip size, including all probing pads, is 0.64 mm × 0.57 mm. In addition, standalone RTPS and PI were fabricated and measured for verification. The S-parameters were measured with a Keysight N5227A network analyzer and VDI WR-6.5 extension modules using on-wafer ground-signal-ground (GSG) probes.

Fig. 2 presents the measured insertion loss and phase shift of the 180° RTPS as V_ctrl is varied from −1 to 1 V, with a 0.1-V step. The average loss ranges from 11.9 dB to 13.3 dB over the frequency range of 130–160 GHz. In addition, as shown in Fig. 2(b), a continuous phase shift of at least 180° is achieved. The simulated maximum phase shift, overlaid in Fig. 2(b) as a solid red line with symbols, shows good agreement with the measurement.

Fig. 2

Measured results of (a) insertion loss and (b) phase shift of the RTPS.

Fig. 3(a) demonstrates the measured gain of the PI. The peak gain is −5.4 dB and −5.6 dB at 143.6 GHz for the 0° and 180° states, respectively. Furthermore, Fig. 3(b) shows that the measured amplitude imbalance and phase difference between the two states remained less than 0.3 dB and 4.8°, respectively, within the 130–160 GHz range.

Fig. 3

Measured results of (a) gain, (b) amplitude imbalance, and phase difference of the PI.

Fig. 4(a) depicts the measured gain of the proposed phase shifter at 16 phase states. The peak gain is −12.1 dB at 147.2 GHz, along with a 3-dB bandwidth of 17.5 GHz, within the 136.2–153.7 GHz range. Moreover, although the gain was compromised during the design process to achieve the low DC power consumption of 12 mW, it can be increased by adding extra amplifier stages at the expense of higher DC consumption. Fig. 4(a) also illustrates the root-mean-squared (RMS) amplitude error of the proposed phase shifter. Under 4-bit resolution, the RMS amplitude error is 1.8 dB at 145 GHz, and it remains below 2 dB from 136.2 to 153.7 GHz. The measured phase shift is presented in Fig. 4(b), demonstrating that a continuous phase shift of at least 360° is achieved over a 3-dB bandwidth. Furthermore, the input and output matching performance are shown in Fig. 4(c) and Fig. 4(d), respectively. The input and output return losses are more than 10 dB from 130 to 160 GHz and from 142.1 to 156.7 GHz, respectively. Notably, discrepancies between the measurement and simulation results presumably originated from unavoidable inaccuracies in the varactor model, probing pads, and electromagnetic coupling at high frequencies.

Fig. 4

Measured results of (a) gain and RMS amplitude error, (b) phase shift, (c) input matching, and (d) output matching of the proposed phase shifter.

In Table 1, the proposed phase shifter is compared to previously reported Si-based phase shifters. It is evident that compared to other active phase shifters [1–6], the one proposed in this work consumes the lowest DC power while covering a small chip area. Furthermore, unlike passive phase shifters [7, 8], it achieves a continuous full 360° phase shift. Furthermore, the overall performance of the proposed phase shifter was evaluated using the following figure-of-merit (FOM):

Table 1

Performance comparison with previously reported Si-based phase shifters

(1) FOM=f0[GHz]·Gpeak[lin.].BW3dB[GHz]RMSp,3dB[deg]·RMSa,3dB[lin.]·PDC[mW]·Core size[mm2],

where f₀ is the center frequency, G_peak is the peak gain, BW₃_dB is the 3-dB bandwidth, RMS_p_,3_dB is the RMS phase error in BW₃_dB, and RMS_a_,3_dB is the RMS amplitude error in BW₃_dB. Owing to the low DC power consumption and compact core size of the proposed phase shifter, this work achieved a competitive FOM compared to prior works.

IV. Conclusion

A D-band phase shifter was fabricated using 65-nm CMOS technology. By combining RTPS and PI, the phase shifter achieved a continuous full 360° phase shift, along with low DC power consumption and moderate insertion loss. Furthermore, compared to prior research, this work achieved a competitive FOM. Overall, the proposed phase shifter can be employed in D-band phased-array systems owing to its full 360° phase shift and low DC power consumption.

Notes

This work was supported by the Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MIST) (No. RS-2021-II210260, Research on LEO Inter-Satellite Links).

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