A Novel Direct-Binary Amplitude Modulator Integrated with a 16-Times Frequency Multiplier for 5G+ Applications
Article information
Abstract
This article presents a novel passive direct binary amplitude modulator (AM) integrated with two frequency multipliers (FMs) and a drive amplifier. Both FMs are composed of a harmonic generator and a modified cascode buffer, along with an additional single-to-differential amplifier added in front of the first FM. The input frequency band (1.5–1.75 GHz) is up-converted to the intermediate frequency band of 4–5 GHz by the first FM, while the second FM up-converts the IF band to the target millimeter wave band of 24–28 GHz. Furthermore, the mm-wave amplitude is directly modulated by a capacitor ladder whose ratio is digitally programmable. This unique capacitor-ladder structure AM is employed to attain uniformly distributed constellation points and improve the output signal-to-noise ratio. The proposed modulator is fabricated on a 65-nm CMOS with a die size of 0.73 mm2. When applying the modulator to I/Q paths, 1.33% error vector magnitude for 256-QAM was measured at 26 GHz.
I. Introduction
For 5G and 5G+ communication systems, it has been established that 24–86 GHz carrier frequency, 3 GHz data bandwidth at 39 GHz, and a modulation order of up to 256-QAM should be assigned to achieve a maximum data rate of 24 Gbps [1–3]. To achieve industrial demands for fast data rates, securing a wide communication data bandwidth and a high modulation/ demodulation order is crucial. According to the Nyquist criterion (D = 2Blog2M) and Shannon’s theorem (D = Blog2(1 + SNR)), when the modulation order (M) is 256-QAM, the maximum data rate (D) should be 48 Gbps, and the minimum required signal-to-noise ratio (SNR) must be 48 dB. However, accomplishing 48 dB SNR would be too difficult for a classical direct-converting modulator, such as a chain of wideband CMOS in-phase/quadrature (I/Q) digital-to-analog converters (DACs) and up-converting mixers.
To address this issue, six-port-based passive millimeter-wave (mm-wave) modulators have been intensively researched owing to their capability of directly modulating binary data [4, 5]. One of the advantages of the direct binary modulator is that it can substitute for wideband I/Q DACs and up-converting mixers. More importantly, the modulator’s output SNR is significantly improved due to the absence of flicker and thermal noises of wideband I/Q DACs and mixers. However, the error vector magnitude (EVM) of such modulators cannot be easily improved since their reflection coefficients are nonlinearly related to impedance loads. Moreover, multilateral effects among ports become more severe at high frequencies, such as in the mm-wave. As a result, a small impedance change at any port would likely influence the S-parameters of the other ports. In addition, I/Q mismatch, port-to-port isolation, and I/Q crosstalk are unexpectedly varied at different data modulations, making it very difficult to maintain the reflected magnitude as planned. Therefore, the six-port-based modulator cannot accomplish high-order modulation while maintaining equally and uniformly spaced constellation points at the mm-wave.
Furthermore, the synthesizer phase noise for mm-wave 5G wireless communication needs to be very low to achieve less than 100 fs integrated RMS jitter from 12 kHz to 20 MHz for implementing more than 256-QAM data, as described in [6]. However, the low quality factor of both the inductor and capacitor (C) makes it difficult to design an ultra-low mm-wave. Phase noise LC tuned voltage-controlled oscillator (VCO) to meet the stringent integrated RMS jitter requirements for 5G communication systems. To address this, the cascade local oscillator (LO) generator topology has been strongly recommended and successfully proposed for lower-frequency synthesizers and frequency multipliers (FMs) used in wireless communication systems beyond 5G+ [7] to achieve the required LO RMS jitter performance [8–11].
This paper presents a novel passive direct-binary amplitude modulator (AM) integrated with a 16-times FM that is optimized for the harmonic rejection ratio (HRR) of the modified double balance mixer-type FMs developed in [12–14]. The proposed AM structure is a good fit for ensuring the same amplitude difference for all between two close modulated magnitudes. In other words, the normalized output amplitude of the AM can be programmed from −15 to 15, with increments of 2, to provide 16 states with a 4-bit control. Therefore, if the proposed AM is individually applied to both I/Q paths, an accurate linear step 256-QAM modulation can be accomplished. Furthermore, its EVM is substantially improved compared to that of a six-port-based modulator.
This article is organized as follows. In Section II, the proposed AM with a 16-times FM is introduced, and its core circuitries are explained. Section III describes the chip fabrication process and the measurement results. In addition, a brief analysis of the test results for phase noise degradation due to frequency multiplication, HRR characteristics, and EVM performance is presented in this section. A summary and comparative analysis of the proposed AM with recently published papers in the field are provided in Section IV.
II. Topology and Circuit Design
1. Topology
As shown in Fig. 1(a), the proposed modulator is composed of a single-to-differential (S2D) amplifier, two FMs in cascade connection, a novel 4-bit capacitor ladder-based AM, and a drive amplifier (DA). The output frequencies of both the first and second FM resonate at quadruple the frequency of each input frequency. As a result, the total frequency multiplication factor of the FMs is 16, resulting in a 24–28 GHz output frequency (fout) when an input frequency (fin) is applied in the 1.5–1.75 GHz band. The same topology, comprising a harmonic generator (HG) and a modified cascade buffer (BUF), is employed for both FMs. The BUF output of each FM is parallelly connected to an automatic constant amplitude control loop (ACACL), which guarantees the convergence of each output amplitude to the programmable reference voltage while also preventing oscillation.
Block diagram of (a) the proposed modulator and (b) QAM modulator.
The output amplitude of the second FM in the 24–28 GHz band is modulated proportionally to the two capacitors ratio, which can be programmed by 4 digital bits. Therefore, the AM output amplitude can be selected from among 16 different levels, depending on the 4-bit state. The AM amplitude can be increased by the minimum level (Amin) whenever the 4-bit state is changed from k to k + 1. In other words, if the 4-bit magnitude is increased by the less significant bit (LSB), the amplitude difference would be Amin. Finally, using the two proposed AMs with external input/output I/Q couplers and baluns, as shown in Fig. 1(b), the target 256-QAM direct binary modulation can be linearly performed.
2. Circuit Design
The schematic of the proposed S2D amplifier is shown in Fig. 2(a). As described in [15], a conventional S2D amplifier is characterized by a parallel connection between the common-gate (CG) and common-source (CS) stages. The CG (M2) stage provides wideband input matching, while the CS (M1) stage inverts the input signal to impose a 180º phase change. To attain a fully differential output, the delay of the CG and CS stages must be the same, and their gain magnitude should be equal. By properly adjusting the sizes of M1, M2, and Cc2 and slightly differentiating the CG stage current from the CS stage current, less than 1 dB and 1º phase error were confirmed by simulation. Other CG stages (M3 and M4) are added to isolate the output from the input and reduce the Miller effect. The S2D output (Vout) is tuned using an inductor (Lp) and a 5-bit binary weighted C-bank, which divides the entire frequency band into 32 sub-bands. The impedance at the low resonant frequency is decreased by adding the turn-on resistance of the switch to degrade the L-C tank quality (Q) factor, as shown in Fig. 2(b). Therefore, to enhance the L-C tank parasitic parallel resistor, Rp, a negative-gm pair is added. The equivalent parallel resistances of the Rp and −2/gm can be expressed as follows:
(a) Schematic of single-to-differential amplifier with input matching, (b) output impedance without equalization, and (c) output impedance with equalization.
where NRp = 2/gm. According to (1), Reg will be more than Rp as long as N is greater than 1. Hence, if N is close to 1, Reg approaches infinity. However, the negative-gm pair starts to oscillate when N is very close to 1, which must be prevented. The output impedance can be equalized by applying a 5-bit digitally controlled current source of the negative-gm (Fig. 2(c)). The S2D input is matched for the 1.5–1.75 GHz band using two stages of L–C–L T-match, with the worst S11 value being −10 dB.
Fig. 3 shows a schematic of the proposed push-pull DA composed of pad capacitance (Cpad) and a bond wire inductor (LBW). Since a bare chip is bonded to the printed circuit board (PCB), the DA output is placed close to the PCB pad to reduce the DA output bond wire inductance. Consequently, the bond wire inductance was estimated to be just 0.35 nH, while the S2D input bond wire inductance was calculated to be 1.3 nH. Furthermore, the device sizes of M1–M4 were appropriately set to generate small parasitic capacitances for a wide frequency bandwidth. Notably, the DA occupies a relatively small die area, since it does not have an inductor. Its output is matched to 50 Ω using an external passive BALUN (BAL-0036) using two stages of C–L–C Pi-match, with the worst S22 value being −9 dB for 24–28 GHz.
Schematic of push-pull drive amplifier with output matching.
The HG employed in this study maintains the same topology applied in [12–14]. This paper follows the design procedure described in [12], in which the HG generated a relatively stable fourth output current harmonic. However, while the current mirror type bias was applied to all HGs in [12], in this study, the tail current, IT, bias is added to the first HG to prevent common mode spurs from converting into differential spurs, as shown in Fig. 4. Notably, due to a lower frequency input than the second FM input frequency, the adjacent harmonic of the first HG is too close to be sufficiently suppressed by the output load of the Lp and the 5-bit C-bank. Therefore, HRR improvement using the tail current is considered more efficient. Moreover, Ioffn and Ioffp current sources are added to the common nodes of the M3–M4 and M5–M6 differential pairs to fix the asymmetry caused by possible mismatches in the transistors, resistors, and capacitors. In effect, the HRR at the ±fin offset from the required harmonic is improved.
Schematic of harmonic generator.
Similar to the proposed S2D amplifier, the HG output band is divided into 32 sub-bands by a 5-bit C-bank. The HRR of each sub-band is optimized by individually adjusting the current of the negative-gm differential pair, termed Q-Enhancer in Fig. 4.
The buffer (BUF) topology presented in [12–14] is adopted in the proposed modulator. Notably, tail current is applied to the first FM’s buffer for HRR improvement, as shown in Fig. 5(a). Furthermore, a negative-gm differential pair is added parallel to the cascode amplifier output. In addition, an ACACL is attached to each buffer output to maintain a constant output amplitude, ensuring the best possible optimization of the building blocks that follow, such as the HG and AM.
(a) Buffer with ACACL and (b, c) ACACL process variation simulation.
Since an HG is a naturally nonlinear circuit, it cannot be guaranteed that the required harmonic power will increase and unwanted harmonic powers will be suppressed by an input voltage swing, be it big or small. Instead, it ensures that there is always a certain input amplitude at a certain current to provide the best HRR. Therefore, the first FM output should be equipped with an ACACL to provide the necessary constant amplitude for the second HG.
Needless to say, the AM input must also be constant to accurately program the direct binary output amplitude. Therefore, an ACACL must be applied at the output of the second FM.
When comparing the buffer output peak, Vpeak, to the reference voltage, Vref, regulated by the bandgap reference, if the former is larger than the latter, the tail current of the negative-gm pair decreases, causing N in (1) to increase. This indicates that the buffer output swing declines as N/(N – 1) decreases. In contrast, the buffer output swing increases when Vpeak is smaller than Vref. At the end of the loop convergence, the peak voltage is expected to be close to the reference voltage, maintained by an ACACL. Fig. 5(b) and 5(c) show the results of ACACL simulations for two extreme PVT variations—one being an FF process with a 2.75 V power supply at −20°C and the other being an SS process with a 2.25 V power supply at 100°C. The Vpeak amplitudes converge to the Vref reference voltage (0.7 V) at 2.0 μs, with the corresponding differential output swings being stably constant.
Fig. 6 presents a schematic of the proposed novel AM, where the output amplitude can be directly modulated by programming the 4-bit data (‘D4D3D2D1’). Two identical C-banks are connected in a ladder structure. The digital control bits, Dks, are applied to the top C-bank, while the complement digital control bits,
Proposed amplitude modulator.
Here,
By superposing (2) and (3), Voutp can be expressed in terms of Vin and Vinp as follows:
Similarly, the negative output, Voutn, can be calculated as:
By subtracting (5) from (4) and dividing it by (Vinp–Vin), the transfer function of the proposed AM, TAM, can be formulated as follows:
Therefore, when the digital control bit stream, D4–D1, is set to ‘0000’, the numerator of TAM would be
However, the numerator capacitance varies for each digital state. Table 1 lists all the calculated numerator capacitances of TAM for the 16 different D4–D1 states.
D4D3D2D1 states versus amplitude modulator output magnitudes
Therefore, if
Naturally, slight differences in capacitance should be expected between the two capacitors integrated into the close silicon die area. At a capacitor ratio error over ±3σ, the process variation would be less than about ±0.5%, which can be easily verified by simulation using currently available CMOS processes.
III. Chip Fabrication and Test
As shown in Fig. 7, the proposed modulator is fabricated on 65-nm CMOS with a die size of 0.73 mm2, excluding the I/O pads. The FMs occupy more than 2/3 of the entire chip area. The 4-bit capacitor ladder occupies only 0.05 mm2 of area, while the DA occupies minimal die area. A central reference current (CRC) and a serial peripheral interface (SPI) are also integrated. Power supply and ground were allocated to the first FM, the second FM, the ACACLs, the AM, and the DA. Furthermore, each FM’s HG and BUF are equipped with an individual power supply and ground. Notably, the main reason for separating their power supply and ground is to isolate the substrate multilaterally using guard ring around each building block.
Die micrograph of the proposed modulator.
A block diagram of the chip test setup is shown in Fig. 8. The input signal over the 1.5–1.75 frequency band was generated using Keysight N5183B. The AM output was measured by employing Keysight E4448A, with Keysight E3631A being the power supply for the test PCB. The chip was evaluated by programming a CPU to control the device under test (DUT) through the SPI.
Block diagram of the test setup.
The measured average power consumption of the first and second FMs was 3 mW and 2 mW, respectively. Notably, more power was consumed by the first FM due to the use of a 2.5 V power supply to secure a sufficient headroom for overcoming the voltage drop caused by the tail current. In contrast, a 1.2 V power supply was applied to the second FM. Furthermore, the ACACL power consumption of the first and second FMs was 0.4 mW and 0.8 mW, respectively. Overall, the average power consumption of the proposed AM was negligible. The CRC consumed 0.8 mW. Overall, the total power consumption by the proposed AM was 7 mW. The push-pull DA driving 50-Ω consumed 9 mW of power for −15 dBm output.
As shown in Fig. 9, the measured phase noise degradation between the input and output of the 16-times FM is about 24.3 dB at 24 GHz and 28 GHz output frequencies, similar to the mathematical phase noise deterioration values obtained (24 dB = 20log(16)). In other words, the proposed FMs add negligible phase noise to the input signal. Furthermore, the output frequencies of two HRRs were measured at 24 GHz and 28 GHz. Fig. 10 shows that the worst HRR of more than 62.9 dBc occurs at 2fin offset from the required harmonic, indicating that the guard rings applied to the presented FMs, as shown in Fig. 7, improved the HRR by more than 10 dB compared to the worst HRR noted in [12]. Moreover, significant frequencyrelated spurs are observed despite the immense effort dedicated to ensuring a symmetric topology and layout. Therefore, the nearest tone adjacent to the required harmonic is considered the fundamental tone (fin). Fortunately, its HRR was improved by the current sources, Ioffn and Ioffp, to reach more than 72 dBc, as shown in Fig. 4.
Phase noise degradation: (a) 24 GHz and (b) 28 GHz.
HRR measurements: (a) 24 GHz and (b) 28 GHz.
Fig. 11 shows the measured constellation plots of 64/256 QAMs when 1.625 GHz input frequency is applied. Each constellation plot represents the individual crowd measurement results for 100 data points programmed by the SPI. An active AM normally provides the widest noise-like crowd plot at the largest output magnitude since the output noise is highest at this point. In contrast, the proposed modulator shows an almost constant crowd plot for all the different points because of its noiseless characteristics. Furthermore, the constellation points of the proposed AM were more uniformly distributed than those of the other six-port-based modulators. Consequently, it is established that the absence of noise and a uniform distribution lead to better EVM.
Constellation measurements of (a) 65-QAM and (b) 256-QAM.
IV. Comparison and Conclusion
Recently, six-port-based modulators have been researched to directly modulate binary data. The most significant benefit of the six-port modulator is that it can substitute wideband I/Q DACs and up-converting mixers, thus reducing power consumption and improving output SNR. However, it cannot sufficiently improve the EVM because the uniform allocation of constellation points is difficult to achieve due to the natural nonlinear relationship between reflection coefficients and loads. Furthermore, since all ports are multilaterally affected, an impedance change at any port would influence the S-parameters of the other ports. Moreover, port-to-port isolation, I/Q crosstalk, and mismatch vary unexpectedly at different data modulation rates, making it difficult to implement high-order QAM data in the mm-wave.
Therefore, high-order modulation and demodulation need to be implemented for extensive data rate requirements that go beyond those of 5G+ wireless communication systems. Moreover, the LO integrated RMS jitter specification is quite stringent for mm-waves. To accomplish the required jitter specification, cascade structures composed of lower-frequency synthesizers and mm-wave FMs have been researched and proposed in the literature.
To solve the above-mentioned six-port problems, as well as to achieve efficient mm-wave FM in terms of HRR, power consumption, and the multiplication factor, a novel AM topology that can be integrated with recently invented mm-wave FMs is proposed in this article. The proposed AM features a unique capacitor-ladder structure with the capability of digitally conducting linear mm-wave amplitude modulation. Theoretically, the capacitive divider output does not depend on frequency— it depends only on the capacitor ratio. As a result, implementing a wideband mm-wave would be an efficient choice. Furthermore, the capacitive ladder structure is the least sensitive to PVT variations (±3σ process, ±10% power supply voltage, and temperature from −20°C to 100°C) compared to other topologies.
To the authors’ knowledge, no previous paper has explored the integration of chips in direct binary AM and mm-wave FM. Hence, the performance of the proposed AM is evaluated with respect to FM and direct binary AM. In Table 2, the proposed AM is compared with recently published papers as an FM [14, 16, 17]. The FM in [14] involves the lowest power consumption and the largest frequency bandwidth (BW) percentage but has the worst HRR. In contrast, the proposed AM attained the largest frequency multiplication (M) and HRR, leading to the best figure-of-merit (FoM), as noted in the last row of Table 2. Furthermore, its FM output thermal noise floor is −155 dBc/Hz and its OP1 is 1.6 dBm.
Comparison of the proposed antenna performance with that of existing references
Table 3 presents a comparison of recently published state-of-the-art direct binary modulators, including the AM proposed in this paper. Both [4] and [5] constructed six-port-based modulators on PCB patterns. Compared to [4] and [5], a lower EVM (1.33%) and a higher carrier frequency (28 GHz) is achieved by the newly invented AM owing to its several advantages.
Comparison with state-of-the-art direct binary modulators
Acknowledgments
This work was supported by the Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No.2020-0-00216, Development of mmWave Data Conversion Free Phased-Array Tx Based on 6PMP). The Eda tool was supported by the IC Design Education Center (IDEC), Korea.
References
Biography
Kyu-Hyun Nam, https://orcid.org/0000-0003-1584-3150 received B.S., M.S., and Ph.D. degrees in electrical engineering from Kookmin University, Seoul, South Korea, in 2012, 2014, and 2022, respectively. He is currently a Post-doctoral Research Fellow in electrical engineering, at Kookmin University, Seoul, South Korea. His research interests include RF/Microwave/mm-wave wireless communication systems and RF, analog, and mixed-mode circuit designs.
Nam-Pyo Hong, https://orcid.org/0000-0001-5493-6435 received B.S., M.S., and Ph.D. degrees from the School of Electrical Engineering, Chung-Ang University, Seoul, South Korea, in 2007, 2009, and 2015, respectively. From 2015 to 2018, he was a Postdoctoral Research Fellow in electrical engineering, at Kookmin University, Seoul, South Korea. He was a senior researcher with the ICT device and Packing research center, at Korea Electronics Technology Institute (KETI), from 2019 to 2020. He is currently a research professor at Kookmin University. His research interests include RF, analog, and mixed-mode circuit designs for mobile communication.
Jun-Seok Park, https://orcid.org/0000-0002-4223-7706 received his B.S., M.S., and Ph.D. degrees from Kookmin University, Seoul, Korea, in 1991, 1993, and 1996, respectively, all in electronics engineering. In 1997, he was a senior researcher in the Department of Electrical Engineering at the University of California at Los Angeles (UCLA). From 1998 to 2003, he was an assistant professor in the Information Technology Engineering Division at Soon-chunhyang University, Asan, Korea. He is currently a professor in the Department of Electrical Engineering at Kookmin University. In 2009, he was invited as an associate professor to the California Institute of Technology (Caltech) as part of a research expert group, where he contributed to many low-noise/high-speed system/platform research activities. From 2019 to 2013, he was a member of the key expert group for IoT convergence (Brain Korea 21 program), where he collaborated with several core design groups for wireless power transfer and energy charger systems and platforms. During the same period, he led the National Engineering and Science R&D group (Ministry of Land, Infrastructure, and Transport) to develop stationary power platforms for electric vehicles. From 2015 to 2017, he was a committee member of the Smart Sensor Network R&D group for safety control. From 2017 to 2020, he was in the R&D committee group of the Korea Energy Agency for the development of ESS-based uniform networks. Recently, he led the Future 5G Convergence and Computing Technology program of the Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) to develop high-performance phased array systems. His research interests include RF/microwave/mm-wave/THz SoC, MMIC, numeric methodology for integrated metamaterial applications, EBG, DGS, solid-state ground configuration and optimization, low-noise phased array for military/automotive radar systems, and uniform smart RF signal/power circuits driven by machine learning.